Verilog-A和Verilog-AMS为建模和仿真提供了一个新的维度

I. Miller, T. Cassagnes
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引用次数: 12

摘要

Verilog-A为模拟和混合信号电子系统的建模、设计和仿真能力提供了一个新的维度。以前,模拟仿真是基于Spice的,Spice是一个非常有效的仿真环境,它基于晶体管、电阻器和电容器等原语。数字设计验证基于硬件描述语言(HDL)。Verilog和Verilog衍生产品因其易于使用和门级仿真能力而被广泛接受。Verilog在1997年占HDL模拟器销售额的60%以上,拥有大量补充语言并扩展验证和测试能力的工具。本文介绍了Verilog- a语言的动机,Verilog- a语言是Verilog的扩展,用于描述模拟和非电气行为,并通过简短的示例和对喷墨打印机ASIC支持IC行为模型的概述来说明Verilog- a语言。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Verilog-A and Verilog-AMS provides a new dimension in modeling and simulation
Verilog-A provides a new dimension in modeling, design and simulation capability for analog and mixed signal electronic systems. Previously, analog simulation has been based upon Spice, which is a very effective simulation environment based on primitives such as transistors, resistors, and capacitors. Digital design verification is based on a Hardware Description Language (HDL). Verilog and Verilog derivatives have been widely accepted due to their ease of use and gate level simulation capability. Verilog, which accounted for more than 60% of the HDL simulator sales in 1997, has a strong following with a host of tools that complement the language and extend the capability to verification and test. This paper presents the motivation for the Verilog-A language, an extension of Verilog to describe analog and non-electrical behavior, and illustrates the Verilog-A language via short examples and a overview of an ink jet printer ASIC support IC behavioral model.
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