Process considerations in reducing leakage current of PIN radiation detectors

PIN diode structures for radiation detection were designed and fabricated on high resistivity silicon wafers by means of planar process. Technological process development of the device and resulting electrical characteristics are presented. Extrinsic gettering with polysilicon and n/sup +/ phosphorus doped back side layer was employed. Surface passivation with dry or wet thermal oxide in combination with silicon nitride was performed in order to reduce surface leakage current over top p/sup +/ boron doped active area. Moreover, thermal budget was kept as low as possible due to preservation of bulk lifetime. Total leakage current as one of the most adequate parameter to evaluate process was monitored on fabricated radiation detectors and test structures. Best average values of leakage current density achieved were in low nA/cm/sup 2/ range per 100 /spl mu/m depletion width for the case of gettering with LPCVD polysilicon phosphorus doped layer on the rear side.