Verilog-A and Verilog-AMS provides a new dimension in modeling and simulation

Abstract

Verilog-A provides a new dimension in modeling, design and simulation capability for analog and mixed signal electronic systems. Previously, analog simulation has been based upon Spice, which is a very effective simulation environment based on primitives such as transistors, resistors, and capacitors. Digital design verification is based on a Hardware Description Language (HDL). Verilog and Verilog derivatives have been widely accepted due to their ease of use and gate level simulation capability. Verilog, which accounted for more than 60% of the HDL simulator sales in 1997, has a strong following with a host of tools that complement the language and extend the capability to verification and test. This paper presents the motivation for the Verilog-A language, an extension of Verilog to describe analog and non-electrical behavior, and illustrates the Verilog-A language via short examples and a overview of an ink jet printer ASIC support IC behavioral model.