Impact of inductance on timing characteristics of VLSI interconnects

Abstract

As the result of the scaling down of technology and increased chip sizes, the cross-sectional area of wires has been reduced. With these trends, it is becoming crucial to be able to determine which nets within a high speed VLSI circuit exhibit prominent inductive effects. The object of this paper is to answer a question frequently put to designers: is inductance necessary to model interconnections or can a simple RC model be sufficient? By comparing the simulation results obtained from electrical simulations to an electromagnetic approach we can verify if the RC distributed model is always sufficient to characterize the propagation delay and the degradation due to the interconnect lines in submicronic circuit. Limits between RC and RLC models are determined.