Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.最新文献

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RF-MEMS SPDT switch on silicon substrate for space applications RF-MEMS SPDT开关在硅衬底上的空间应用
P. Farinelli, F. Giacomozzi, G. Mannocchi, R. Marcelli, B. Margesin, P. Mezzanotte, S. Di Nardo, P. Russer, R. Sorrentino, F. Vitulli, L. Vietzorreck
{"title":"RF-MEMS SPDT switch on silicon substrate for space applications","authors":"P. Farinelli, F. Giacomozzi, G. Mannocchi, R. Marcelli, B. Margesin, P. Mezzanotte, S. Di Nardo, P. Russer, R. Sorrentino, F. Vitulli, L. Vietzorreck","doi":"10.1109/SMIC.2004.1398190","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398190","url":null,"abstract":"The paper illustrates the activity carried out under an ESA contract for the development of a miniaturized RF-MEMS SPDT switch and switch matrix using micromachining technology on a silicon substrate for power applications. A manufacturing procedure, based on an eight masks process, has been set up. At present, a broadband single-pole-double-throw (SPDT) switch operating in the 0-30 GHz frequency range has been fabricated and measured. Isolation of about -40 dB and insertion loss better than -0.7 dB have been obtained.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117052648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A 47 GHz monolithically integrated SiGe push-push oscillator 一个47 GHz单片集成SiGe推推振荡器
R. Wanner, M. Pfost, R. Lachner, G. Olbrich
{"title":"A 47 GHz monolithically integrated SiGe push-push oscillator","authors":"R. Wanner, M. Pfost, R. Lachner, G. Olbrich","doi":"10.1109/SMIC.2004.1398154","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398154","url":null,"abstract":"We present a monolithically integrated push-push oscillator, fabricated in a production-near SiGe:C bipolar technology. The planar inductors have been simulated by a three dimensional electromagnetic field solver. The oscillator obtains an output power of 0 dBm at 47 GHz, while the fundamental signal at 23.5 GHz is -39 dBm. The single sideband phase noise level at 1 MHz offset frequency is -104 dbc/Hz.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123001771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A generic architecture for multi-modulus dividers in low-power and high-speed frequency synthesis 低功耗高速频率合成中多模分频器的通用结构
Raja K. K. R. Sandireddy, F. Dai, R. Jaeger
{"title":"A generic architecture for multi-modulus dividers in low-power and high-speed frequency synthesis","authors":"Raja K. K. R. Sandireddy, F. Dai, R. Jaeger","doi":"10.1109/SMIC.2004.1398213","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398213","url":null,"abstract":"The paper presents a generic architecture for programmable multi-modulus dividers (MMD) for low-power and high-speed frequency synthesis applications. The proposed architecture uses cascaded divide by 2/3 cells in a ripple fashion except for the last cell, which is a P/(P+1) dual modulus prescaler used to adjust the minimum division ratio and the required division range. This approach provides an optimized architecture with minimum current consumption, the smallest area and minimum number of control bits for designing MMDs with a unit step increment.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123003208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
RF performance degradation in pMOS transistors due to hot carrier and soft breakdown effects 热载流子和软击穿效应导致pMOS晶体管射频性能下降
Yi Liu, A. Sadat, Chuanzhao Yu, J. Yuan
{"title":"RF performance degradation in pMOS transistors due to hot carrier and soft breakdown effects","authors":"Yi Liu, A. Sadat, Chuanzhao Yu, J. Yuan","doi":"10.1109/SMIC.2004.1398231","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398231","url":null,"abstract":"Hot carrier and soft breakdown stress on pMOS RF devices has been examined. The cut-off frequency and the S-parameters degrade with stress. The measured threshold voltage shifts negatively and mobility decreases after stress. It is our understanding that this is the first attempt to investigate hot carrier and soft breakdown effects on RF performance of pMOS transistors and first reporting of negative shift in threshold voltage.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132547935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
GPS low noise amplifier with high immunity to wireless jamming signals GPS低噪声放大器,抗无线干扰能力强
F. Gruson, H. Schulz, Hans-Joachim Golberg, H. Schumacher, M. Durler, S. Spiegel
{"title":"GPS low noise amplifier with high immunity to wireless jamming signals","authors":"F. Gruson, H. Schulz, Hans-Joachim Golberg, H. Schumacher, M. Durler, S. Spiegel","doi":"10.1109/SMIC.2004.1398171","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398171","url":null,"abstract":"A SiGe GPS low noise amplifier with power control option and high immunity to wireless jamming signals is presented. These novel features applied to Atmel's ATR0610 GPS LNA allow significant power saving at the radio interface while meeting the out-of-band linearity requirements. The results show a noise figure of 2 dB, including the embedded pre-select filter, and an out-of-band IIP/sub 3/ above +8 dBm in the frequency range between 1.8 GHz and 2 GHz with 3 mA current consumption. The GPS system performance shows a GPS sensitivity below -141 dBm with 5 ms integration interval.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125606500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling and characterization of integrated passive elements for applications in silicon high frequency systems 硅高频系统中集成无源元件的建模与表征
R. Caverly, T. Walsh, J. Reifsnyder, S. Pearson
{"title":"Modeling and characterization of integrated passive elements for applications in silicon high frequency systems","authors":"R. Caverly, T. Walsh, J. Reifsnyder, S. Pearson","doi":"10.1109/SMIC.2004.1398206","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398206","url":null,"abstract":"A methodology for robust integrated circuit passive element modeling has been developed. The methodology was used to design process-independent structures in a silicon CMOS process and combined a number of techniques and software packages to ensure run-to-run stability of element values. Experimental data verifying the techniques is presented.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116880574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A direct method to extract the substrate resistance components of RF MOSFETs valid up to 50 GHz 一种直接提取有效频率高达50 GHz的射频mosfet衬底电阻分量的方法
Seyoung Kim, Jeonghu Han, Hyungcheol Shin
{"title":"A direct method to extract the substrate resistance components of RF MOSFETs valid up to 50 GHz","authors":"Seyoung Kim, Jeonghu Han, Hyungcheol Shin","doi":"10.1109/SMIC.2004.1398211","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398211","url":null,"abstract":"A direct method to extract the substrate resistance components of RF MOSFETs has been proposed. The method predicts the output characteristics of MOSFETs accurately up to 50 GHz, while the model with a single substrate resistance was valid up to 15 GHz.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"345 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124282808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A high efficient dual path power amplifier for IS-95 CDMA handset applications 为IS-95 CDMA手机应用设计的高效双路功率放大器
Y. Kang, K.S. Jin, S. Kim, J. Lee, S.G. Kim, Y. Kim
{"title":"A high efficient dual path power amplifier for IS-95 CDMA handset applications","authors":"Y. Kang, K.S. Jin, S. Kim, J. Lee, S.G. Kim, Y. Kim","doi":"10.1109/SMIC.2004.1398187","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398187","url":null,"abstract":"A highly efficient dual path power amplifier (PA) for IS-95 code division multiple access (CDMA) handset applications is proposed. A dual path PA consists of two different size PAs combined parallely with single input/output matching circuits. The dual path PA operates in two different modes, a high power mode and a low power mode (lower than 16 dBm). A dual path PA is fabricated in an InGaP/GaAs heterojunction bipolar transistor (HBT) monolithic micro-wave integrated circuit (MMIC) for the 1.76 GHz Korea Personal Communication Service (K-PCS), and operates at a supply voltage of 3.4 V. The dual path PA exhibits an output power of 29 dBm, a 46 % power added efficiency (PAE) at 28 dBm output power, and a -39 dBc adjacent channel power ratio (ACPR) at a 1.25 MHz offset frequency in the high power mode and an output power of 24 dBm, a 19 % PAE at a 16 dBm output power level, and a -58 dBc ACPR at a 1.25 MHz offset frequency in the low power mode.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114242538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modeling of distortion in bipolar transistors - a review 双极晶体管的畸变建模综述
M. Schroter, P. Sakalas, H. Tran
{"title":"Modeling of distortion in bipolar transistors - a review","authors":"M. Schroter, P. Sakalas, H. Tran","doi":"10.1109/SMIC.2004.1398185","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398185","url":null,"abstract":"An overview on modeling HF distortion in bipolar transistors is given. \"Modeling\" includes theoretical investigations, which are generally applicable to bipolar transistors, as well as compact models and their experimental verification for recent SiGe technologies. Also, 1D device simulation results provide additional insight into the mechanisms.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115311080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A manufacturable high-k MIM dielectric with outstanding reliability and voltage linearity for RF and mixed-signal technologies 一种可制造的高k MIM电介质,具有出色的可靠性和电压线性度,适用于射频和混合信号技术
K. Vaed, E. Eshun, R. Bolam, K. Stein, D. Coolbaugh, D. Ahlgren, J. Dunn
{"title":"A manufacturable high-k MIM dielectric with outstanding reliability and voltage linearity for RF and mixed-signal technologies","authors":"K. Vaed, E. Eshun, R. Bolam, K. Stein, D. Coolbaugh, D. Ahlgren, J. Dunn","doi":"10.1109/SMIC.2004.1398166","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398166","url":null,"abstract":"We demonstrate the simultaneous optimization of 100,000 POH reliability and voltage linearity (<40 ppm/V) for a high-k MIM dielectric (4.5 fF/m/sup 2/) that is both Al and Cu BEOL compatible. Also, we discuss the scaling of dielectric films to achieve excellent bias linearity, while attaining a capacitance density of 7.2 fF/m/sup 2/.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122538461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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