A generic architecture for multi-modulus dividers in low-power and high-speed frequency synthesis

Abstract

The paper presents a generic architecture for programmable multi-modulus dividers (MMD) for low-power and high-speed frequency synthesis applications. The proposed architecture uses cascaded divide by 2/3 cells in a ripple fashion except for the last cell, which is a P/(P+1) dual modulus prescaler used to adjust the minimum division ratio and the required division range. This approach provides an optimized architecture with minimum current consumption, the smallest area and minimum number of control bits for designing MMDs with a unit step increment.