{"title":"High-performance bottom-gate poly-Si/SiN TFTs on glass-substrate","authors":"K. Shimizu, O. Sugiura, M. Matsumura","doi":"10.1109/IEDM.1992.307449","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307449","url":null,"abstract":"Bottom-gate poly-Si/SiN TFTs have been presented with extremely high electron mobility of more than 300 cm/sup 2//Vs on a glass-substrate, for the first time. These TFTs can be produced by the standard process for the bottom-gate a-Si/SiN TFTs with only two additional excimer-laser annealings, that is, the laser pre-annealing of the SiN gate and the dual-beam annealing of an active thin silicon layer.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"31 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131539292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Hida, M. Tokushima, M. Fukaishi, T. Maeda, Y. Ohno
{"title":"A 0.25 mu m inner sidewall-assisted super self-aligned gate heterojunction FET fabricated using all dry-etching technology for low voltage controlled LSIs","authors":"H. Hida, M. Tokushima, M. Fukaishi, T. Maeda, Y. Ohno","doi":"10.1109/IEDM.1992.307591","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307591","url":null,"abstract":"The first successful fabrication is reported for a high performance 0.25 mu m T-shaped gate pseudomorphic heterojunction FET without the conventional electron-beam lithography and wet etching technology, which often cause long turn-around times and poor reproducibility and controllability, resulting in big obstacles to producing GaAs LSIs. The novel device structure and fabrication process enables realizing very low power consumption GaAs VLSIs superior to even future Si LSIs, and have the following advantages. (i) 0.25 mu m gate formation by optical (stepper) lithography and anisotropic dry etching for SiO/sub 2/ sidewalls, and smaller gate formation by an increase in sidewall thickness. (ii) Stable refractory metal gate electrode with low stress and high reliability. (iii) Low resistance T-shaped gate electrode of refractory and low resistivity multilayer metals. (iv) Small R/sub s/ and R/sub d/ due to ohmic electrodes self-aligned to T-shaped gate electrode, leading to small current saturation voltage V/sub dss/, indispensable for low supply voltage controlled-LSIs. (v) Low damage dry etching of insulating films using low power magnetron ion etching. (vi) Formation of E/D-FETs with different V/sub T/ using selective dry etching of GaAs to AlGaAs. (vii) High reproducibility and uniformity due to all dry etching technology.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128240583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Browning, C. Chan, J. Ye, R. Macgregor, T. Ruden
{"title":"Measurement of end-hat effects in a crossed-field amplifier","authors":"J. Browning, C. Chan, J. Ye, R. Macgregor, T. Ruden","doi":"10.1109/IEDM.1992.307468","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307468","url":null,"abstract":"A linear format, low frequency (150 MHz), low power (10 to 100 W), crossed-field amplifier is operated with variable bias, electrostatic confining electrodes (end-hats). The end-hat bias is found to cause electron transport only in the vicinity of the end-hats. End-hat current measurements indicate a substantial part of the electron beam current (40%) can be collected when the end-hats are biased more positive than the floating potential. The observed change in gain versus end-hat bias can be accounted for by the lost beam current. Device gain versus sole bias measurements have been compared with numerical simulations and give general agreement.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121118882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The effects of furnace N/sub 2/O annealing on MOSFETs","authors":"Z. Liu, J. Krick, H. Wann, P. Ko, C. Hu, Y. Cheng","doi":"10.1109/IEDM.1992.307438","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307438","url":null,"abstract":"MOSFETs with 70-110 AA thick furnace N/sub 2/O-annealed gate oxides are examined at both room and liquid nitrogen temperatures. The N/sub 2/O anneal not only improves device performance, e.g. by increasing the high normal field mobility and current drivability, but it also suppresses degradation induced by Fowler-Nordheim and channel hot-carrier injection. Random telegraph noise measurements reveal a possible correlation between the interface properties and the mobility.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114936512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Universal description of hot-carrier-induced interface states in NMOSFETs","authors":"R. Woltjer, G. Paulzen","doi":"10.1109/IEDM.1992.307418","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307418","url":null,"abstract":"In NMOSFETs, hot-carrier-induced damage primarily consists of interface states. We present a new model to predict interface state formation over the full gate voltage range. To this end we add an empirical oxide-field dependence to the \"lucky-electron\" model. Furthermore, we establish the relation between interface states and the degradation of transistor parameters. We checked both new models experimentally with many degradation experiments (including charge pumping) at various stress voltages on NMOSFETs of 0.2-2.0 mu m gate length and 5.5-25 nm oxide thickness with either conventional drain or LDD.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"5 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120812224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel analog-to-digital conversion architecture using electron waveguides","authors":"C. Eugster, P. Nuytkens, J. D. del Alamo","doi":"10.1109/IEDM.1992.307409","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307409","url":null,"abstract":"We have demonstrated a novel analog-to-digital (A:D) conversion architecture based on the quantized conductance of electron waveguides. In our scheme, a dual electron waveguide (DWG) device implements a binary quantizer and encoder for one significant bit. The conductance values of the on and off states are 2e/sup 2//h and zero, respectively. By cascading multiple DWG devices, higher order bits can be attained. In this paper, we demonstrate the first significant bit and the second significant bit for a 2-bit analog-to-digital converter using a DWG device fabricated in an AlGaAs/GaAs modulation-doped heterostructure.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134434362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Bonani, G. Ghione, C. Naldi, R. D. Schnell, H. Siweris
{"title":"HEMT short-gate noise modelling and parametric analysis of NF performance limits","authors":"F. Bonani, G. Ghione, C. Naldi, R. D. Schnell, H. Siweris","doi":"10.1109/IEDM.1992.307429","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307429","url":null,"abstract":"The paper describes an analytical, CAD-oriented quasi-2D noise model for AlGaAs-GaAs HEMTs, based on an improved version of the Ando and Itoh approach (see IEEE Trans. on Electron Devices, vol. ED-37, no. 1, p. 67-78, 1990). The model was validated through comparison with DC, AC and noise measurements carried out on both standard 0.5 mu m (HEMT30) and advanced 0.25 mu m (HEMT40) SIEMENS HEMTs. On the basis of the SIEMENS HEMT structure, a scaling study was performed to extrapolate the performance limits of this technology with decreasing gate length in the range 0.5-0.1 mu m. The extension of the model to pseudomorphic and double-channel HEMT's is in progress.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"34 1-2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132089645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Stress-induced current in thin silicon dioxide films","authors":"R. Moazzami, C. Hu","doi":"10.1109/IEDM.1992.307327","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307327","url":null,"abstract":"Low-field current following Fowler-Nordheim stress of thin gate oxides is studied. The conduction mechanism is attributed to trap-assisted tunneling of electrons. For oxides thicker than 100 AA, this stress-induced current is observed to decay as traps are filled without significant tunneling out of traps. In thinner oxides, steady-state current flows when there is an equilibrium between trap filling and emptying processes. This model is observed to be consistent with stress-induced current behavior in a wide range of oxide thicknesses (60 AA to 130 AA) and process technologies.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132425528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Ganci, J. Hajjar, T. Clark, P. Humphries, J. Lapham, D. Buss
{"title":"Self-heating in high performance bipolar transistors fabricated on SOI substrates","authors":"P. Ganci, J. Hajjar, T. Clark, P. Humphries, J. Lapham, D. Buss","doi":"10.1109/IEDM.1992.307391","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307391","url":null,"abstract":"The effects of self-heating on the characteristics of bipolar transistors fabricated on silicon-on-insulator (SOI) substrates are discussed through measurements and simulations. It is shown that the SOI substrate's buried oxide affects the thermal characteristics of the transistor. A three fold increase in thermal resistivity is observed on transistors fabricated on SOI substrates over identical transistors fabricated on regular silicon substrates. Moreover, thermal gradients within the device footprint are also discussed and evaluated both experimentally and using MEDICI simulations. Finally, a simple thermal model is presented which predicts transistor characteristics with good accuracy.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"8 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130203844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multiple-gate split-drain MOSFET magnetic-field sensing device and amplifier","authors":"F. Kub, C. S. Scott","doi":"10.1109/IEDM.1992.307414","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307414","url":null,"abstract":"A new split-drain MOSFET magnetic-field sensing device is reported which uses multiple gates to establish a longitudinal electric field in the channel. A relative sensitivity of 185 mA/AT was measured for a double-polysilicon, multiple-gate, split-drain MOSFET. A triple-drain multiple-gate MOSFET device achieved relative sensitivities greater then 10,000 mA/AT. A new amplifier circuit for the multiple-gate, split-drain device achieved an absolute sensitivity of 10 V/T at a 400 nA bias current corresponding to a relative sensitivity of 2.5*10/sup 7/ V/AT. The intrinsic power dissipation of the magnetic amplifier sensor is as small as 8 mu W.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134490538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}