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Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting最新文献

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An 850 MHz current feedback operational amplifier 850兆赫电流反馈运算放大器
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274080
S. Jost
{"title":"An 850 MHz current feedback operational amplifier","authors":"S. Jost","doi":"10.1109/BIPOL.1992.274080","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274080","url":null,"abstract":"A monolithic DC-to-850 MHz, low-distortion current feedback operational amplifier fabricated in a complementary bipolar bonded wafer technology is described. Discussed are an approach for achieving low-input offset voltage without sacrificing common-mode range or gain bandwidth; design for expected package and board parasitics; the use of low-overhead, high-impedance signal mirrors in the gain stage; and inverting input bias current cancellation. The output clamp is described. A summary of the circuit's performance obtained from production and bench testing on multiple fabrication lots is presented.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131587345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Characterization of low VAR bipolar transistors using a revised SPICE simulator 使用改进的SPICE模拟器表征低VAR双极晶体管
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274044
G. Neaves, J. White, M. Burnham, A. Zlotnicka, R. Pryor
{"title":"Characterization of low VAR bipolar transistors using a revised SPICE simulator","authors":"G. Neaves, J. White, M. Burnham, A. Zlotnicka, R. Pryor","doi":"10.1109/BIPOL.1992.274044","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274044","url":null,"abstract":"The approximation of the Gummel-Poon base width modulation term, q1, that is implemented in conventional versions of SPICE, is discussed. The impact of the approximation of the characterization of low VAR bipolar transistors is described. Comparisons of simulated to measured curves demonstrate the improved accuracy which results from using the unapproximated q1 term. Use of the unapproximated q1 term produces physically meaningful Early voltage parameters and improved simulation accuracy.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117099345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An analytical model for collector currents in gated lateral bipolar transistors 门控侧双极晶体管集电极电流的解析模型
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274046
K. Joardar
{"title":"An analytical model for collector currents in gated lateral bipolar transistors","authors":"K. Joardar","doi":"10.1109/BIPOL.1992.274046","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274046","url":null,"abstract":"A physically based, analytical model for collector currents in lateral bipolar junction transistors is presented and used to describe the hybrid mode operation of these devices in the presence of a gate electrode over the base region. Results obtained from the analytical model are compared with those of computer simulations. Good agreement has been demonstrated with both numerical simulations and experimental data.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123136173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Noise reduction techniques for an ECL-CMOS RAM with a 2 ns write cycle time 写周期为2ns的ECL-CMOS RAM的降噪技术
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274057
K. Ohhata, Y. Sakurai, H. Nambu, K. Kanetani, Y. Idei, T. Hiramoto, N. Tamba, K. Yamaguchi, M. Odaka, K. Watanabe, T. Ikeda, N. Homma
{"title":"Noise reduction techniques for an ECL-CMOS RAM with a 2 ns write cycle time","authors":"K. Ohhata, Y. Sakurai, H. Nambu, K. Kanetani, Y. Idei, T. Hiramoto, N. Tamba, K. Yamaguchi, M. Odaka, K. Watanabe, T. Ikeda, N. Homma","doi":"10.1109/BIPOL.1992.274057","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274057","url":null,"abstract":"An ultra-high-speed ECL-CMOS static RAM (SRAM) with a cycle time of 2 ns has been developed. To achieve fast cycle time, three noise reduction techniques are proposed: which are a noise reduction clamp circuit for reducing the Y-select signal noise; a critical damping emitter follower for the overshoot noise; and a twisted-bit line structure with a normally on equalizer for the bit line crosstalk. The authors describe the noise generation mechanisms and the operation of circuits using each of the techniques. Experimental results are also described.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131839637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Microwave performance of InGaAs/InP composite collector bipolar transistors InGaAs/InP复合集电极双极晶体管的微波性能
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274090
A. Feygenson, R. Hamm, P.R. Smith, R. Montgomery, D. Ritter, R.D. Yadvish, H. Temkin
{"title":"Microwave performance of InGaAs/InP composite collector bipolar transistors","authors":"A. Feygenson, R. Hamm, P.R. Smith, R. Montgomery, D. Ritter, R.D. Yadvish, H. Temkin","doi":"10.1109/BIPOL.1992.274090","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274090","url":null,"abstract":"A composite collector heterostructure InGaAs/InP bipolar transistor (CCHBT) is described. The collector design assures both the high breakdown voltage, BV/sub CEO/, and the high speed needed for practical IC applications. The microwave performance of the CCHBT is presented. The authors have fabricated and tested monolithic transimpedance amplifiers based on these composite collector transistors. A bandwidth of 28 GHz and a gain of 40 dB Omega were obtained.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133836811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
3.3 volt sense-amplifier schemes suitable for 4 Mb BiCMOS SRAMs 3.3伏感测放大器方案适用于4mb BiCMOS ram
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274055
A. Suzuki, H. Kato, T. Kobayashi, T. Hamano, K. Sato, M. Matsui, Y. Urakawa, K. Ochii
{"title":"3.3 volt sense-amplifier schemes suitable for 4 Mb BiCMOS SRAMs","authors":"A. Suzuki, H. Kato, T. Kobayashi, T. Hamano, K. Sato, M. Matsui, Y. Urakawa, K. Ochii","doi":"10.1109/BIPOL.1992.274055","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274055","url":null,"abstract":"The authors propose and discuss sense amplifiers suitable for low voltage operation. Compared with a conventional current sensing scheme, the hierarchical voltage sensing scheme reduces sensing delay by 39% and improves functional minimum voltage to 1.8 V, which is sufficiently low for a 3.3-V static RAM (SRAM). High-speed sensing techniques for 4-Mb VLSI SRAMs and beyond, and performance of a 9-ns, 4-Mb transistor-transistor-logic input/output SRAM implementing one of these sense amplifiers, are also presented.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121926898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Circuit design for a 15-Gb/s Si bipolar decision circuit 15gb /s Si双极判决电路的电路设计
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274063
K. Ishii, H. Ichino, Y. Kobayashi, C. Yamaguchi
{"title":"Circuit design for a 15-Gb/s Si bipolar decision circuit","authors":"K. Ishii, H. Ichino, Y. Kobayashi, C. Yamaguchi","doi":"10.1109/BIPOL.1992.274063","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274063","url":null,"abstract":"The authors have designed and fabricated a high-bit-rate and high-input-sensitivity decision circuit using an advanced super-self-aligned Si bipolar process technology by 0.5- mu m photolithography. To realize both a very high bit rate and a high input sensitivity at the same time required not only advanced device technology but also a sophisticated circuit design to extract the maximum performance from the device. The circuit design included optimization of individual transistor sizes to boost the speed and adoption of a wideband preamplifier to enhance the sensitivity. The circuit operates at up to 15 Gb/s with an input sensitivity of 40 mV/sub p-p/.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"176 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114158710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A stacked emitter polysilicon (STEP) bipolar technology for 16 Mb BiCMOS SRAMs 用于16mb BiCMOS ram的堆叠发射极多晶硅(STEP)双极技术
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274074
H. Suzuki, T. Nishigori, T. Yamazaki, K. Nakamura, T. Oguri, T. Atsumo, M. Takada, A. Ikemoto
{"title":"A stacked emitter polysilicon (STEP) bipolar technology for 16 Mb BiCMOS SRAMs","authors":"H. Suzuki, T. Nishigori, T. Yamazaki, K. Nakamura, T. Oguri, T. Atsumo, M. Takada, A. Ikemoto","doi":"10.1109/BIPOL.1992.274074","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274074","url":null,"abstract":"A stacked emitter polysilicon (STEP) bipolar technology is described for megabit BiCMOS static RAMs (SRAMs) using TFT (thin film transistor) load cells. The STEP electrode structure consists of the gate (bottom) and the channel (top) polysilicon layers of the TFT. This technology overcomes the perimeter and plug effects for narrow emitter windows. A tungsten-silicide ground line in the RAM cell can be employed to realize a highly stable cell operation at 3.3 V in a 16-Mb BiCMOS SRAM.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115652139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 15.5 GHz bandwidth Si bipolar preamplifier 一种15.5 GHz带宽Si双极前置放大器
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274061
H. Kitahata, H. Takemura, T. Suzaki, M. Soda, T. Morikawa, H. Tezuka, C. Ogawa, S. Fujita, T. Tashiro
{"title":"A 15.5 GHz bandwidth Si bipolar preamplifier","authors":"H. Kitahata, H. Takemura, T. Suzaki, M. Soda, T. Morikawa, H. Tezuka, C. Ogawa, S. Fujita, T. Tashiro","doi":"10.1109/BIPOL.1992.274061","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274061","url":null,"abstract":"The authors describe an extremely high performance Si bipolar preamplifier, which has a 15.5-GHz bandwidth with a transimpedance gain of 52 dB Omega . To achieve such high performance, the optimization of feedback parameters in the circuit and the realization of the 46-GHz f/sub max/ (maximum frequency of oscillation) transistor were carried out simultaneously. The circuit consists of gain and buffer stages. Employing a dual-feedback configuration in the gain stage design, the preamplifier has broadband and low-noise characteristics. The measured frequency response of the preamplifier, using the optimized circuit and the improved transistors, is shown.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128115662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A quad low voltage rail-to-rail operational amplifier 四极低压轨对轨运算放大器
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274041
R. Vyne, T. Petty, R. Koda, D. Susak
{"title":"A quad low voltage rail-to-rail operational amplifier","authors":"R. Vyne, T. Petty, R. Koda, D. Susak","doi":"10.1109/BIPOL.1992.274041","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274041","url":null,"abstract":"A low-voltage rail-to-rail amplifier that has a NPN PNP switchable differential input stage allowing rail-to-rail input voltage swings is presented. The inputs can be overdriven without causing phase reversal in the output signal. The amplifier provides rail-to-rail output voltage swings which extend to within 50 mV of either rail. The output stage is current boosted to provide up to 50 mA of drive current.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124361117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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