L. Wagner, K.M. Kim, P. Nguyen, M. J. Saccamango, B. Cunningham, K. DeVries, S. Ratanaphanyarat, S. Fischer, J. Snare, A. Lucchese, P. Strugazow, P. Peressini, S. Chu, R. Knepper
{"title":"Modeling the small-emitter effect in polysilicon-emitter transistors","authors":"L. Wagner, K.M. Kim, P. Nguyen, M. J. Saccamango, B. Cunningham, K. DeVries, S. Ratanaphanyarat, S. Fischer, J. Snare, A. Lucchese, P. Strugazow, P. Peressini, S. Chu, R. Knepper","doi":"10.1109/BIPOL.1992.274067","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274067","url":null,"abstract":"Arsenic shadowing, which is an important consideration for the small-emitter effect in bipolar polysilicon-emitter transistors, was simulated using two-dimensional process and device modeling tools. Results are compared with data for conventional and epi-base polysilicon-emitter technologies. Consideration is also given to other parameters that affect the base current. This analysis shows that the principle features of the arsenic shadowing effect can be modeled and explained by using the simulation tools. These simulations showed that the small-emitter effect was still present in the more advanced epi-base devices.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117247688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A sub-nanosecond 9-bit accurate ECL comparator using cascaded complementary gain stages","authors":"T. Stetzler, T.E. Flemming, I. Koullias","doi":"10.1109/BIPOL.1992.274065","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274065","url":null,"abstract":"A 960-ps propagation delay, 0.5-mV-offset-voltage, emitter-coupled-logic (ECL)-compatible comparator with increased common mode range was designed and fabricated in the CBIC-V complementary bipolar process featuring 10-GHz NPN and 4.3-GHz PNP transistors. This low-offset, subnanosecond comparator was implemented in a semicustom linear array designed for high-performance circuits. Cascaded complementary gain stages using a modified emitter-coupled pair amplifier design permits operation from 3 V to 10 V supplies with less than 100-ps dispersion. A summary of the comparator experimental results is given.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126723334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Streutker, A. Pruijmboom, D. Klaassen, J. Slotboom
{"title":"Thermionic emission limited recombination in phosphorus-implanted polysilicon emitters","authors":"G. Streutker, A. Pruijmboom, D. Klaassen, J. Slotboom","doi":"10.1109/BIPOL.1992.274084","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274084","url":null,"abstract":"Bipolar transistors with P-implanted polysilicon emitters have been fabricated with high emitter efficiency and low emitter series resistance. Temperature-dependent measurements showed that the base current was limited by thermionic emission over a potential barrier of 220 MeV at the polysilicon-monosilicon interface. Due to this effective barrier, the base current was dominated by recombination in the monosilicon emitter. A model which explains the base current and its dependence on the temperature is presented. The difference between the P-doped and As-doped transistor is attributed to the fact that for the latter the base current is not limited by thermionic emission.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129702227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Ratnam, M. Grubisich, B. Mehrotra, A. Iranmanesh, C. Blair, M. Biswal
{"title":"The effect of isolation edge profile on the leakage and breakdown characteristics of advanced bipolar transistors","authors":"P. Ratnam, M. Grubisich, B. Mehrotra, A. Iranmanesh, C. Blair, M. Biswal","doi":"10.1109/BIPOL.1992.274070","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274070","url":null,"abstract":"The authors describe the effect of the isolation edge profile on the leakage and breakdown characteristics of advanced poly emitter NPN bipolar transistors. It is shown that the isolation edge profile can cause considerable base narrowing and reduction of the Gummel number, thus controlling the collector-emitter breakdown voltage, BV/sub ceo/, and the collector-emitter leakage current, I/sub ceo/. The reduction in BV/sub ceo/ can become severe enough so that the devices cannot operate at the maximum supply voltages used in emitter coupled logic (ECL) and BiCMOS circuits. The vertical scaling of the intrinsic device will be constrained under these circumstances to meet the required circuit breakdown characteristics, compromising device parameters such as beta and the unity gain cutoff frequency. Therefore device isolation can control key device parameters, thus becoming a major limiting factor in the development of high-performance bipolar devices.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123211340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An accurate quasi-static method for determining the excess phase shift in the base region of bipolar transistors","authors":"J. S. Hamel","doi":"10.1109/BIPOL.1992.274049","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274049","url":null,"abstract":"The conventional quasi-static approach has been extended to enable the accurate calculation of the phase shift of the common emitter current gain up to the transition frequency solely from static charge distributions for bipolar transistors with arbitrary base impurity profiles. Accurate knowledge of the phase shift allows the use of simple, yet accurate, high-frequency compact bipolar transistor models which use this information to determine critical model parameters. The accuracy of this approach was assessed by AC numerical simulation. The ability of the approach to estimate the phase shift of the common emitter current gain from static charge distributions allows accurate predictive high-frequency AC modeling of both digital and analog bipolar and BiCMOS circuits without the need for high-frequency, time-dependent device simulation or high-frequency device measurements.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124141956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"BiCMOS analog arbitration circuits","authors":"K. Bracken, L. R. Carley","doi":"10.1109/BIPOL.1992.274040","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274040","url":null,"abstract":"The authors describe a family of BiCMOS circuits for use in the sequence detection electronics of a magnetic recording channel. The discussion focuses on a class of analog BiCMOS circuits that implement the arbitration function. Several BiCMOS analog arbitration circuit topologies were evaluated. General design equations were derived for each topology in terms of power consumption. These equations were used to design circuits. The performance of these circuits was evaluated and compared to the predictions. Simulation and experimental results confirmed the design equations. The end result is a family of BiCMOS metric arbitration circuits for an analog implementation of a maximum likelihood sequence detection (MLSD) algorithm.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125462804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simulation of bipolar VLSI circuits using overlapped relaxation technique","authors":"M.E. Mokari, W. Fang","doi":"10.1109/BIPOL.1992.274045","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274045","url":null,"abstract":"A fast and robust overlapped waveform relaxation (OWR) algorithm is presented for transient simulation of bipolar VLSI circuits. From the simulation results, it can be concluded that by using the OWR algorithm, the speedup can be two orders of magnitude compared to direct SPICE-like methods for very large circuits. Four representative examples, including combinational and sequential digital circuits as well as an analog bipolar circuit, are included. It is shown that the OWR algorithm is twice as fast as the waveform relaxation algorithm.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"109 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124177815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Polysilicon-emitter bipolar transistors with interfacial nitride","authors":"F. Nouri, B. Scharf","doi":"10.1109/BIPOL.1992.274077","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274077","url":null,"abstract":"Polysilicon emitter transistors with interfacial nitride and low emitter resistance have been fabricated reproducibly. The use of a phosphorus emitter has reduced the emitter resistance to a level comparable to that of barrier-free poly emitters. It is shown that the enhanced gain due to the interfacial barrier can be traded off for a reduction in base resistance. The authors have investigated the thermal stability, electrical reliability and noise characteristics of the transistors.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128464157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Futurebus+ central arbiter based on pairwise mutual exclusion","authors":"C. Dike, F. Ostler","doi":"10.1109/BIPOL.1992.274052","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274052","url":null,"abstract":"A scheme for building low-latency, first-come, first-served arbiters is presented. The basis of the scheme is pairwise mutual exclusion, which provides a fire wall for considerations of metastability. Cycles can occur, requiring a resolution mechanism, of which two are presented. A 14-channel, 7-ns arbiter for Futurebus+ has been fabricated in BiCMOS technology.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121579091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Pelella, P. Nguyen, M.J. Saccamango, S. Ratanaphanyarat, J. Comfort, S. Fischer, R. Knepper, P.P. Peressini, S. Chu
{"title":"A comparative device and performance analysis between a Si-Ge epitaxial-base HBT and a Si double-poly I/I BJT npn structure","authors":"M. Pelella, P. Nguyen, M.J. Saccamango, S. Ratanaphanyarat, J. Comfort, S. Fischer, R. Knepper, P.P. Peressini, S. Chu","doi":"10.1109/BIPOL.1992.274085","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274085","url":null,"abstract":"The device characteristics and performance leverage of a SiGe epitaxial-base heterojunction bipolar transistor (HBT) are compared to those of an advanced Si double-poly ion-implanted (I/I)-base bipolar junction transistor (BJT) npn structure. In addition, a collector-base profile optimization for the SiGe device structure is described. Two-dimensional numerical process and device simulators and a lumped equivalent circuit model generator are used for the comparison along with experimental data. The simulated results show a greater than 3* increase in current gain, a 1.5* increase in the unity-gain cutoff frequency, and a 13% improvement in ECL circuit delay for the SiGe device. The experimental results confirm the device behavior predicted by the simulations.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"247 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116156838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}