{"title":"使用级联互补增益级的亚纳秒9位精确ECL比较器","authors":"T. Stetzler, T.E. Flemming, I. Koullias","doi":"10.1109/BIPOL.1992.274065","DOIUrl":null,"url":null,"abstract":"A 960-ps propagation delay, 0.5-mV-offset-voltage, emitter-coupled-logic (ECL)-compatible comparator with increased common mode range was designed and fabricated in the CBIC-V complementary bipolar process featuring 10-GHz NPN and 4.3-GHz PNP transistors. This low-offset, subnanosecond comparator was implemented in a semicustom linear array designed for high-performance circuits. Cascaded complementary gain stages using a modified emitter-coupled pair amplifier design permits operation from 3 V to 10 V supplies with less than 100-ps dispersion. A summary of the comparator experimental results is given.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A sub-nanosecond 9-bit accurate ECL comparator using cascaded complementary gain stages\",\"authors\":\"T. Stetzler, T.E. Flemming, I. Koullias\",\"doi\":\"10.1109/BIPOL.1992.274065\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 960-ps propagation delay, 0.5-mV-offset-voltage, emitter-coupled-logic (ECL)-compatible comparator with increased common mode range was designed and fabricated in the CBIC-V complementary bipolar process featuring 10-GHz NPN and 4.3-GHz PNP transistors. This low-offset, subnanosecond comparator was implemented in a semicustom linear array designed for high-performance circuits. Cascaded complementary gain stages using a modified emitter-coupled pair amplifier design permits operation from 3 V to 10 V supplies with less than 100-ps dispersion. A summary of the comparator experimental results is given.<<ETX>>\",\"PeriodicalId\":286222,\"journal\":{\"name\":\"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-10-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.1992.274065\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1992.274065","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A sub-nanosecond 9-bit accurate ECL comparator using cascaded complementary gain stages
A 960-ps propagation delay, 0.5-mV-offset-voltage, emitter-coupled-logic (ECL)-compatible comparator with increased common mode range was designed and fabricated in the CBIC-V complementary bipolar process featuring 10-GHz NPN and 4.3-GHz PNP transistors. This low-offset, subnanosecond comparator was implemented in a semicustom linear array designed for high-performance circuits. Cascaded complementary gain stages using a modified emitter-coupled pair amplifier design permits operation from 3 V to 10 V supplies with less than 100-ps dispersion. A summary of the comparator experimental results is given.<>
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