A sub-nanosecond 9-bit accurate ECL comparator using cascaded complementary gain stages

T. Stetzler, T.E. Flemming, I. Koullias
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引用次数: 1

Abstract

A 960-ps propagation delay, 0.5-mV-offset-voltage, emitter-coupled-logic (ECL)-compatible comparator with increased common mode range was designed and fabricated in the CBIC-V complementary bipolar process featuring 10-GHz NPN and 4.3-GHz PNP transistors. This low-offset, subnanosecond comparator was implemented in a semicustom linear array designed for high-performance circuits. Cascaded complementary gain stages using a modified emitter-coupled pair amplifier design permits operation from 3 V to 10 V supplies with less than 100-ps dispersion. A summary of the comparator experimental results is given.<>
使用级联互补增益级的亚纳秒9位精确ECL比较器
采用CBIC-V互补双极工艺,采用10 ghz NPN和4.3 ghz PNP晶体管,设计并制造了一款传输延迟960-ps、偏移电压0.5 mv、兼容发射器耦合逻辑(ECL)、共模范围更大的比较器。这种低偏置,亚纳秒比较器是在为高性能电路设计的半定制线性阵列中实现的。级联互补增益级使用改进的发射器耦合对放大器设计,允许从3 V到10 V电源工作,色散小于100 ps。对比较器的实验结果进行了总结。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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