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Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting最新文献

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SOI: opportunities and challenges for sub-0.25 mu m VLSI SOI: 0.25 μ m以下VLSI的机遇与挑战
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274038
G. Shahidi
{"title":"SOI: opportunities and challenges for sub-0.25 mu m VLSI","authors":"G. Shahidi","doi":"10.1109/BIPOL.1992.274038","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274038","url":null,"abstract":"It is argued that, as VLSI minimum feature size is reduced down to the 0.25- mu m regime and below, utilization of silicon-on-insulator (SOI) as the substrate offers a number of key advantages over bulk silicon. Scaling of the room-temperature CMOS is rapidly approaching its limits. SOI devices in the 0.25- mu m regime and below show significant performance improvements compared with bulk CMOS. This suggests that SOI substrates could provide the highest performance room-temperature CMOS, provided a number of outstanding problems are solved. SOI also has a clear advantage over bulk for low-temperature (77 K) operation at a reduced voltage. In bipolar technology, SOI allows realization of devices with no parasitic junction capacitance, sub-0.25 mu m emitter widths, easy isolation, and CMOS-like density. Ease of isolation on SOI allows easy integration of MOS and bipolar devices.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125149629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A method of measuring base and emitter resistances of AlGaAs/GaAs HBTs 一种测量AlGaAs/GaAs HBTs基极和发射极电阻的方法
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274050
S. Prasad
{"title":"A method of measuring base and emitter resistances of AlGaAs/GaAs HBTs","authors":"S. Prasad","doi":"10.1109/BIPOL.1992.274050","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274050","url":null,"abstract":"The author describes a method of determining the base and emitter resistances of AlGaAs/GaAs heterojunction bipolar transistors (HBTs) at a given bias from the S-parameter measurements at a single frequency. The base resistance values agree closely with the calculated values based on layout and sheet resistance considerations. The emitter resistance values agree with those obtained by the open collector method. The method is simple and elegant and can be applied to other bipolar devices as well. No special structures or additional measurements are required for this method.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132639321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Sub-micron BiCMOS process design for manufacturing 亚微米BiCMOS工艺设计制造
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274079
C. K. Lau, C. Lin, D. Packwood
{"title":"Sub-micron BiCMOS process design for manufacturing","authors":"C. K. Lau, C. Lin, D. Packwood","doi":"10.1109/BIPOL.1992.274079","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274079","url":null,"abstract":"A 0.5- mu m BiCMOS process is used to illustrate the details in process design needed as a prerequisite for success in manufacturing. An existing CMOS process was used as the core for the BiCMOS process; CMOS design rules and performance were not altered by the addition of the bipolar processes. Issues related to bipolar integration, individual process modules, interactions between CMOS and bipolar, and manufacturability are discussed in detail. The specific performance targets for the bipolar devices are outlined. This process has been targeted to be used in building future high-performance ASIC products.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"249 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114801564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A semi-physical bipolar transistor model for the design of very-high-frequency analog ICs 设计高频模拟集成电路的半物理双极晶体管模型
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274047
H. Rein, M. Schroter, A. Koldehoff, K. Worner
{"title":"A semi-physical bipolar transistor model for the design of very-high-frequency analog ICs","authors":"H. Rein, M. Schroter, A. Koldehoff, K. Worner","doi":"10.1109/BIPOL.1992.274047","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274047","url":null,"abstract":"A compact transistor model that is well suited for the design of very-high-frequency analog ICs and advanced narrow-emitter transistors is presented. It takes into account non-quasi-static transistor behavior and HF emitter current crowding as well as emitter-periphery and high-current effects. Modeling of the transit time, the base resistance, and the emitter junction capacitance was improved. Besides the simulation of HF analog ICs, the model proved to be well suited for simulating the switching behavior of high-speed digital ICs.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122987421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
UHF-1: a high speed complementary bipolar analog process on SOI UHF-1:在SOI上的高速互补双极模拟过程
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274037
C. Davis, G. Bajor, J. Butler, T. Crandell, J. Delgado, T. Jung, Y. Khajeh-Noori, B. Lomenick, V. Milam, H. Nicolay, S. Richmond, T. Rivoli
{"title":"UHF-1: a high speed complementary bipolar analog process on SOI","authors":"C. Davis, G. Bajor, J. Butler, T. Crandell, J. Delgado, T. Jung, Y. Khajeh-Noori, B. Lomenick, V. Milam, H. Nicolay, S. Richmond, T. Rivoli","doi":"10.1109/BIPOL.1992.274037","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274037","url":null,"abstract":"A complementary silicon bipolar process has been developed for high-performance analog applications. The process features high-frequency PNP and NPN transistors with transition frequencies above 5 GHz and 9 GHz, respectively. The transistors have a double polysilicon, self-aligned structure which is isolated by using bonded wafer silicon-on-insulator (SOI) technology and vertical trenches. The circuit components are interconnected with two levels of metallization. The UHF-1 process has been used to create several advanced analog high-frequency integrated circuits in a monolithic form.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126086977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Simulation of hot electron induced degradation in silicon bipolar transistors 硅双极晶体管热电子诱导降解的模拟
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274066
C. Huang, T. Grotjohn, D. Reinhard, C.J. Sun, C.-C.W. Yu
{"title":"Simulation of hot electron induced degradation in silicon bipolar transistors","authors":"C. Huang, T. Grotjohn, D. Reinhard, C.J. Sun, C.-C.W. Yu","doi":"10.1109/BIPOL.1992.274066","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274066","url":null,"abstract":"A hot electron degradation model for bipolar transistors is presented which calculates the damage on a spatially-dependent, two-dimensional, microscopic level. The model first uses a hydrodynamic transport model to calculate the hot electron current density. Then the number of active interface states formed by these hot electrons is determined and the surface recombination velocity is found. Using the surface recombination velocity, the degraded characteristics and subsequent device lifetime of the bipolar transistor are determined. The model has utility in the prediction of device lifetime degradation due to hot electrons as the geometry, doping profile, temperature and stressing/operating conditions are varied.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128341679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 22 Gb/s decision circuit and a 32 Gb/s regenerating demultiplexer IC fabricated in silicon bipolar technology 采用硅双极技术制作了22gb /s的判决电路和32gb /s的再生解复用器集成电路
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274062
J. Hauenschild, A. Felder, M. Kerber, H. Rein, L. Schmidt
{"title":"A 22 Gb/s decision circuit and a 32 Gb/s regenerating demultiplexer IC fabricated in silicon bipolar technology","authors":"J. Hauenschild, A. Felder, M. Kerber, H. Rein, L. Schmidt","doi":"10.1109/BIPOL.1992.274062","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274062","url":null,"abstract":"A decision circuit and a 1:2 regenerating demultiplexer, which are key components in optical-fiber transmission links, were fabricated in an advanced self-aligning silicon bipolar technology using 0.8- mu m lithography. Maximum speed rather than low power consumption was the main goal of these designs. The transistors were individually optimized using a semiphysical transistor model for circuit simulation. At such high operating speeds the influence of the metal lines on the chip has to be taken into account. Worst-case conditions, caused, e.g., by fabrication spread and variation of the junction temperature, were met. The measured data rates of 22 Gb/s for the decision circuit and 32 Gb/s for the demultiplexer, with excellent retiming capability, have not yet been achieved with any semiconductor technology.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"203 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122434888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Application of base drift field measurement to processing optimization of advanced bipolar transistors 基漂移场测量在先进双极晶体管工艺优化中的应用
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274048
R. Yan, T.M. Liu, J. Sung, W. Possanza, M. A. Prozonic, A. Laduca, T. Chiu
{"title":"Application of base drift field measurement to processing optimization of advanced bipolar transistors","authors":"R. Yan, T.M. Liu, J. Sung, W. Possanza, M. A. Prozonic, A. Laduca, T. Chiu","doi":"10.1109/BIPOL.1992.274048","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274048","url":null,"abstract":"A technique for directly measuring the base drift field in bipolar transistors has been developed and used to study the effects of various base-formation and emitter drive-in conditions on the effective base drift field, a major factor determining the unity-current-gain cutoff frequency f/sub T/, has been studied. Measurements of base drift fields created with these drive-in conditions revealed that insufficient thermal treatment leaves a large portion of the base region with a retarding field, producing low base drift fields and low f/sub T/'s. An appropriate thermal treatment creates a monotonically varying base profile with large drift fields and therefore high f/sub T/'s.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127230147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A complete and consistent electrical/thermal HBT model 一个完整和一致的电/热HBT模型
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274051
C. McAndrew
{"title":"A complete and consistent electrical/thermal HBT model","authors":"C. McAndrew","doi":"10.1109/BIPOL.1992.274051","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274051","url":null,"abstract":"GaAs heterojunction bipolar transistor (HBT) circuits with significant self-heating must be analyzed using coupled electrical and thermal simulation. The author presents a complete, consistent, coupled electrical/thermal model for such devices. The model is applicable to DC, AC, transient large-signal steady-state, noise and stability analyses. Examples of the effects of self-heating on device performance are given. The coupled model is necessary to model GaAs HBT behavior properly when devices are biased at high power dissipation.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125416240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Power partition and emitter size optimisation for bipolar ECL circuit 双极ECL电路的功率分配和射极尺寸优化
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI: 10.1109/BIPOL.1992.274058
H. Hsieh, K. Chin, C. Chuang
{"title":"Power partition and emitter size optimisation for bipolar ECL circuit","authors":"H. Hsieh, K. Chin, C. Chuang","doi":"10.1109/BIPOL.1992.274058","DOIUrl":"https://doi.org/10.1109/BIPOL.1992.274058","url":null,"abstract":"The authors describe an automated approach for optimizing the performance of a bipolar emitter-coupled logic (ECL) circuit. A quadratic equation representing an approximate surface is used to express the circuit delay in terms of the power partition and current densities in the current-switch and the emitter-follower stages. During the iteration of the optimization process, the optimum obtained from the present approximate surface is used as the nominal points for the next iteration. As the nominal point converges to the optimum, the approximate surface converges to a section of the real optimum surface. This methodology transforms the circuit optimization into a multivariable optimization problem and is shown to provide an optimum design with circuit analysis accuracy. The design considerations for a high-performance ECL circuit are also discussed.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123757686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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