SOI: opportunities and challenges for sub-0.25 mu m VLSI

It is argued that, as VLSI minimum feature size is reduced down to the 0.25- mu m regime and below, utilization of silicon-on-insulator (SOI) as the substrate offers a number of key advantages over bulk silicon. Scaling of the room-temperature CMOS is rapidly approaching its limits. SOI devices in the 0.25- mu m regime and below show significant performance improvements compared with bulk CMOS. This suggests that SOI substrates could provide the highest performance room-temperature CMOS, provided a number of outstanding problems are solved. SOI also has a clear advantage over bulk for low-temperature (77 K) operation at a reduced voltage. In bipolar technology, SOI allows realization of devices with no parasitic junction capacitance, sub-0.25 mu m emitter widths, easy isolation, and CMOS-like density. Ease of isolation on SOI allows easy integration of MOS and bipolar devices.<>