Power partition and emitter size optimisation for bipolar ECL circuit

The authors describe an automated approach for optimizing the performance of a bipolar emitter-coupled logic (ECL) circuit. A quadratic equation representing an approximate surface is used to express the circuit delay in terms of the power partition and current densities in the current-switch and the emitter-follower stages. During the iteration of the optimization process, the optimum obtained from the present approximate surface is used as the nominal points for the next iteration. As the nominal point converges to the optimum, the approximate surface converges to a section of the real optimum surface. This methodology transforms the circuit optimization into a multivariable optimization problem and is shown to provide an optimum design with circuit analysis accuracy. The design considerations for a high-performance ECL circuit are also discussed.<>