J. Hauenschild, A. Felder, M. Kerber, H. Rein, L. Schmidt
{"title":"A 22 Gb/s decision circuit and a 32 Gb/s regenerating demultiplexer IC fabricated in silicon bipolar technology","authors":"J. Hauenschild, A. Felder, M. Kerber, H. Rein, L. Schmidt","doi":"10.1109/BIPOL.1992.274062","DOIUrl":null,"url":null,"abstract":"A decision circuit and a 1:2 regenerating demultiplexer, which are key components in optical-fiber transmission links, were fabricated in an advanced self-aligning silicon bipolar technology using 0.8- mu m lithography. Maximum speed rather than low power consumption was the main goal of these designs. The transistors were individually optimized using a semiphysical transistor model for circuit simulation. At such high operating speeds the influence of the metal lines on the chip has to be taken into account. Worst-case conditions, caused, e.g., by fabrication spread and variation of the junction temperature, were met. The measured data rates of 22 Gb/s for the decision circuit and 32 Gb/s for the demultiplexer, with excellent retiming capability, have not yet been achieved with any semiconductor technology.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"203 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1992.274062","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 26
Abstract
A decision circuit and a 1:2 regenerating demultiplexer, which are key components in optical-fiber transmission links, were fabricated in an advanced self-aligning silicon bipolar technology using 0.8- mu m lithography. Maximum speed rather than low power consumption was the main goal of these designs. The transistors were individually optimized using a semiphysical transistor model for circuit simulation. At such high operating speeds the influence of the metal lines on the chip has to be taken into account. Worst-case conditions, caused, e.g., by fabrication spread and variation of the junction temperature, were met. The measured data rates of 22 Gb/s for the decision circuit and 32 Gb/s for the demultiplexer, with excellent retiming capability, have not yet been achieved with any semiconductor technology.<>