Noise reduction techniques for an ECL-CMOS RAM with a 2 ns write cycle time

Abstract

An ultra-high-speed ECL-CMOS static RAM (SRAM) with a cycle time of 2 ns has been developed. To achieve fast cycle time, three noise reduction techniques are proposed: which are a noise reduction clamp circuit for reducing the Y-select signal noise; a critical damping emitter follower for the overshoot noise; and a twisted-bit line structure with a normally on equalizer for the bit line crosstalk. The authors describe the noise generation mechanisms and the operation of circuits using each of the techniques. Experimental results are also described.<>