A stacked emitter polysilicon (STEP) bipolar technology for 16 Mb BiCMOS SRAMs

Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1992-10-07 DOI:10.1109/BIPOL.1992.274074

H. Suzuki, T. Nishigori, T. Yamazaki, K. Nakamura, T. Oguri, T. Atsumo, M. Takada, A. Ikemoto

引用次数: 3

Abstract

A stacked emitter polysilicon (STEP) bipolar technology is described for megabit BiCMOS static RAMs (SRAMs) using TFT (thin film transistor) load cells. The STEP electrode structure consists of the gate (bottom) and the channel (top) polysilicon layers of the TFT. This technology overcomes the perimeter and plug effects for narrow emitter windows. A tungsten-silicide ground line in the RAM cell can be employed to realize a highly stable cell operation at 3.3 V in a 16-Mb BiCMOS SRAM.<>

查看原文本刊更多论文

用于16mb BiCMOS ram的堆叠发射极多晶硅(STEP)双极技术

介绍了一种利用TFT(薄膜晶体管)负载传感器用于兆位BiCMOS静态ram (sram)的堆叠发射极多晶硅(STEP)双极技术。STEP电极结构由TFT的栅极(底部)和沟道(顶部)多晶硅层组成。该技术克服了窄射极窗的周长和塞子效应。在16mb BiCMOS SRAM中，采用硅化钨接地线可以实现3.3 V电压下的高度稳定的电池工作

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting

自引率

0.00%

发文量