{"title":"Circuit design for a 15-Gb/s Si bipolar decision circuit","authors":"K. Ishii, H. Ichino, Y. Kobayashi, C. Yamaguchi","doi":"10.1109/BIPOL.1992.274063","DOIUrl":null,"url":null,"abstract":"The authors have designed and fabricated a high-bit-rate and high-input-sensitivity decision circuit using an advanced super-self-aligned Si bipolar process technology by 0.5- mu m photolithography. To realize both a very high bit rate and a high input sensitivity at the same time required not only advanced device technology but also a sophisticated circuit design to extract the maximum performance from the device. The circuit design included optimization of individual transistor sizes to boost the speed and adoption of a wideband preamplifier to enhance the sensitivity. The circuit operates at up to 15 Gb/s with an input sensitivity of 40 mV/sub p-p/.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"176 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1992.274063","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
The authors have designed and fabricated a high-bit-rate and high-input-sensitivity decision circuit using an advanced super-self-aligned Si bipolar process technology by 0.5- mu m photolithography. To realize both a very high bit rate and a high input sensitivity at the same time required not only advanced device technology but also a sophisticated circuit design to extract the maximum performance from the device. The circuit design included optimization of individual transistor sizes to boost the speed and adoption of a wideband preamplifier to enhance the sensitivity. The circuit operates at up to 15 Gb/s with an input sensitivity of 40 mV/sub p-p/.<>