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[1992] Proceedings The European Conference on Design Automation最新文献

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Energy minimization based delay testing 基于延迟测试的能量最小化
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205939
S. Chakradhar, Mahesh A. Iyer, V. Agrawal
{"title":"Energy minimization based delay testing","authors":"S. Chakradhar, Mahesh A. Iyer, V. Agrawal","doi":"10.1109/EDAC.1992.205939","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205939","url":null,"abstract":"The authors present a novel method for generating robust and non-robust tests for path or gate delay faults in scan and hold type of sequential circuits. The relationship between input and output signal states of a logic gate for an arbitrary pair of input vectors is expressed through an energy function such that minimum-energy states correspond to signal values that are consistent with the gate logic function for both input vectors. The energy function for the circuit is the summation of individual gate energy functions. It implicitly contains information about hazards. For a given delay fault, the energy function is suitably modified so that minimum-energy states are guaranteed to be hazard-free or robust delay tests. Results on sequential benchmark circuit are given.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130600118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Efficient verification of sequential circuits on a parallel system 并行系统上顺序电路的有效验证
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205895
P. Camurati, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
{"title":"Efficient verification of sequential circuits on a parallel system","authors":"P. Camurati, P. Prinetto, M. Rebaudengo, M. Sonza Reorda","doi":"10.1109/EDAC.1992.205895","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205895","url":null,"abstract":"The paper presents a method to verify functional correctness of FSMs on a parallel system. The equivalence condition is expressed in theoretical terms within the framework of the product machine. It consists in proving that a set of states of the product machine is unreachable from the initial reset state. The algorithm is based on state-of-the-art simulation techniques for explicit enumeration on the inputs and is implemented on a parallel machine. The states of the product machine are partitioned for evaluation among available processors. Experimental results show that the method is applicable to real-world circuits and that the parallel version achieves an almost linear speedup in the number of processors.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124656230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware selection and clustering in the HYPER synthesis system 超合成系统的硬件选择与聚类
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205918
C. Chu, J. Rabaey
{"title":"Hardware selection and clustering in the HYPER synthesis system","authors":"C. Chu, J. Rabaey","doi":"10.1109/EDAC.1992.205918","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205918","url":null,"abstract":"A novel approach for the hardware selection and clustering problem in high level synthesis is presented. The goal of the hardware selection is to select a set of hardware modules which minimize the implementation cost of an algorithm, given the timing and throughput constraints. At the same time, simple operators are clustered into large combinatorial blocks to reduce the register count and to increase the throughput. The proposed approach is organized as a search employing a relaxed scheduling for cost estimation and uses a simple, yet accurate timing analysis to verify timing constraints. The results from real applications showed the excellent performance of the proposed algorithm.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124713116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Analog behavioral models for simulation and synthesis of mixed-signal systems 混合信号系统仿真与合成的模拟行为模型
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205978
G. Gielen, E. Liu, A. Sangiovanni-Vincentelli, P. Gray
{"title":"Analog behavioral models for simulation and synthesis of mixed-signal systems","authors":"G. Gielen, E. Liu, A. Sangiovanni-Vincentelli, P. Gray","doi":"10.1109/EDAC.1992.205978","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205978","url":null,"abstract":"A behavioral simulator is shown to be an essential part of a performance-driven hierarchical top-down design strategy for analog blocks within mixed-signal integrated systems. It is used to accurately estimate the performance of the system while down-mapping the specifications over the hierarchy, in order to avoid time-consuming design iterations. It is also indispensable for the final bottom-up verification after completion of the design, as well as for testing purposes. The authors describe the set-up of the generic behavioral models for this simulator, which describe the functional behavior of the analog blocks, independent of the internal architecture. In addition to the nominal behavior, the models also include the important second-order effects (nonidealities, noise, distortion . . .) as well as the statistical variations of most parameters. This is then illustrated in detail for the statistical minimum-rank model of a Nyquist-rate A/D converter. System-level applications show the effectiveness and accuracy of this model.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127637083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Synthesis and optimization of synchronous logic circuits from recurrence equations 基于递归方程的同步逻辑电路综合与优化
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205928
M. Damiani, G. De Micheli
{"title":"Synthesis and optimization of synchronous logic circuits from recurrence equations","authors":"M. Damiani, G. De Micheli","doi":"10.1109/EDAC.1992.205928","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205928","url":null,"abstract":"The paper presents a general solution framework for optimizing synchronous networks across register boundaries. It formulates the problem as that of finding minimum-cost solutions to synchronous recurrence equations. It proposes an algorithm for the solution of such equations that relies on their transformation into a new combinational logic optimization problem. An exact solution algorithm for this problem is presented, and experimental results on synchronous benchmark circuits demonstrate the feasibility of the approach.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"270 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133848163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Transfer free register allocation in cyclic data flow graphs 在循环数据流图中传输自由寄存器分配
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205919
L. Stok
{"title":"Transfer free register allocation in cyclic data flow graphs","authors":"L. Stok","doi":"10.1109/EDAC.1992.205919","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205919","url":null,"abstract":"Discusses an algorithm for the optimal register allocation problem in cyclic data flow graphs. Cyclic data flow graphs result from high level behavioral descriptions that contain loops. Algorithms published up till now did not consider cyclic data flow graphs specifically. When these algorithms are applied to data flow graphs with loops, unnecessary register transfer operations may be introduced. In the paper a new algorithm is presented that performs a minimal register allocation eliminating all superfluous register transfer operations. Experiments on a benchmark set have shown that in all cases all superfluous register transfers could be eliminated at no increase in register cost.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133426118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Automatic formal verification of Cathedral-II circuits from transistor switch level implementation up to high level behavioral specifications by the SFG-tracing methodology 通过sfg跟踪方法对从晶体管开关级实现到高级行为规范的大教堂ii电路进行自动形式化验证
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205893
M. Genoe, L. Claesen, E. Verlind, F. Proesmans, H. de Man
{"title":"Automatic formal verification of Cathedral-II circuits from transistor switch level implementation up to high level behavioral specifications by the SFG-tracing methodology","authors":"M. Genoe, L. Claesen, E. Verlind, F. Proesmans, H. de Man","doi":"10.1109/EDAC.1992.205893","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205893","url":null,"abstract":"Research on the verification of synchronous circuits has been focussed recently on alternative methodologies instead of traditional methods like ad-hoc simulation. Where logic simulation can not avoid the combinatorial explosion that would normally occur when evaluating circuits for each possible input and initial state, new methods such as theorem proving, tautology checking and symbolic simulation are challenges to a more straightforward approach of fully correct circuit design. A new methodology called SFG-Tracing has been developed. It makes use of the concept of ordered binary decision diagrams (OBDDs). This general methodology is currently applied for the automatic verification of the results of the Cathedral Silicon Compilers. For the Cathedral-II system a complete verification environment has been built that allows to verify circuits from transistor switch level up to their high level algorithmic specifications.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132773821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Functional decomposition for universal logic cells using substitution 用代换法对通用逻辑单元进行功能分解
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205889
F. Dresig, P. Lanchès, O. Rettig, U. Baitinger
{"title":"Functional decomposition for universal logic cells using substitution","authors":"F. Dresig, P. Lanchès, O. Rettig, U. Baitinger","doi":"10.1109/EDAC.1992.205889","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205889","url":null,"abstract":"Known synthesis tools with a strong relationship to a library of gates lead to poor results for target architectures based on universal logic cells as basic elements. The authors present an algorithm which uses function substitution in-order to minimize the costs of the decomposed function. Experimental results show an high degree of improvement over other existing synthesis programs.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133317229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Exploiting hierarchy in a cache-based switch-level simulator 在基于缓存的开关级模拟器中利用层次结构
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205924
L. G. Jones
{"title":"Exploiting hierarchy in a cache-based switch-level simulator","authors":"L. G. Jones","doi":"10.1109/EDAC.1992.205924","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205924","url":null,"abstract":"The article presents a caching method that significantly reduces the cost of subnetwork evaluation during switch-level simulation. The method speeds up simulation by as much as a factor of two. While caching may require additional memory it is shown how the structural hierarchy can be exploited to quickly identify subnetworks computing identical functions, merge their cache tables and significantly reduce the memory requirements.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116083925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The effect of multiple charge-discharge paths on testing of BiCMOS logic circuits 多种充放电路径对BiCMOS逻辑电路测试的影响
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205996
K. Roy, M. Levitt, J. Abraham
{"title":"The effect of multiple charge-discharge paths on testing of BiCMOS logic circuits","authors":"K. Roy, M. Levitt, J. Abraham","doi":"10.1109/EDAC.1992.205996","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205996","url":null,"abstract":"Due to the presence of multiple paths to charge or discharge the output node of a BiCMOS logic gate, many of the realistic open and short faults appear as rise or fall time delay faults without changing the functionality of the circuit. Based on circuit level faults, it has been observed that delay fault tests can produce a fault coverage as high as 92% compared to 29% produced by stuck-at tests, for the same set of faults for a BiCMOS inverter. The implications of this dominant failure mode are discussed and a gate level design-for-testability (DFT) scheme is presented.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122104652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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