发布求助
文献互助 智能选刊 最新文献

[1992] Proceedings The European Conference on Design Automation最新文献

筛选
英文 中文
Functional abstraction and formal proof of digital circuits 数字电路的功能抽象与形式化证明
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205976
P. Deverchère, J. Madre, J. Guignet, M. Currat
{"title":"Functional abstraction and formal proof of digital circuits","authors":"P. Deverchère, J. Madre, J. Guignet, M. Currat","doi":"10.1109/EDAC.1992.205976","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205976","url":null,"abstract":"A discussion is given on the set of tools that has been developed at Bull for functional verification of VLSI circuits. The functional verification process is based on two key concepts. The first one is functional abstraction which consists of automatically producing a functional view of a circuit from a lower level of description that can be either a structural or a layout description. The second one is formal verification that consists of automatically proving that the abstracted view of a circuit is correct with respect to its functional specification given by the circuit designer. The set of tools implementing these concepts is intensively used at Bull by all VLSI circuit designers.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116736778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Formalized timing diagrams 形式化时序图
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205958
G. Borriello
{"title":"Formalized timing diagrams","authors":"G. Borriello","doi":"10.1109/EDAC.1992.205958","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205958","url":null,"abstract":"Traditionally, the timing behavior of digital circuits has been described using timing or waveform diagrams. These diagrams concisely represent the shape of the waveforms that are observed at the interface of a circuit and the temporal relationships between their edges. Timing information takes two principal forms: propagation delays that abstract the internal implementation of the circuit and timing constraints that specify how the circuit can be used by its environment. The author proposes a formalization of the concepts and notations used in timing diagrams that enable them to be used in conjunction with hardware description language specifications of the circuit's internal function. WAVES, an interactive timing diagram editor that was designed to embody these formalisms is also described. WAVES is unique in that it captures complex timing behaviour including concurrent, conditional, and iterative event sequences.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116745308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Accurate delay models for ECL logic synthesis ECL逻辑综合的精确延迟模型
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205901
R. Makowitz, A. Wild
{"title":"Accurate delay models for ECL logic synthesis","authors":"R. Makowitz, A. Wild","doi":"10.1109/EDAC.1992.205901","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205901","url":null,"abstract":"The usage of logic synthesis tools for ECL logic has been questionable, among other reasons, because of the discrepancy between the simple, computationally efficient models required by synthesis and the more and more sophisticated models required for accurate simulation. The paper demonstrates that with appropriate choice of modelling parameters, it is possible to map an existing ECL simulation library to a synthesis library with errors below 1%. The authors review the basic delay calculation algorithms provided by a prominent commercial ECL Logic Synthesis tool (Synopsys). They show how delay data is generated by their proprietary delay calculator DECAL. They develop a simplification scheme that enables the algorithms given in Synopsys to produce accurate results. Finally, they present some results on accuracy.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"9 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134288624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A structural optimization method for symbolic FSMs 符号fsm的结构优化方法
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205929
B. Rouzeyre, G. Sagnes, G. Tarroux
{"title":"A structural optimization method for symbolic FSMs","authors":"B. Rouzeyre, G. Sagnes, G. Tarroux","doi":"10.1109/EDAC.1992.205929","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205929","url":null,"abstract":"The paper presents a new structural optimization method for symbolic finite state machines. It is based on the common use of outputs for generating both the next state and the output vectors. An upper bound on the number of shared outputs is given as well as the algorithm giving the best solution.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124420536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ampdes: a program for the synthesis of high-performance amplifiers 放大器:用于合成高性能放大器的程序
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205980
J. Stoffels, C. van Reeuwijk
{"title":"Ampdes: a program for the synthesis of high-performance amplifiers","authors":"J. Stoffels, C. van Reeuwijk","doi":"10.1109/EDAC.1992.205980","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205980","url":null,"abstract":"A circuit synthesis program for high-performance small-signal amplifiers, called Ampdes is described. The synthesis can be done with minimal interaction from the user: only the essential information must be given, and the program will produce a Spice net list and a TEX design report. For a typical design, this takes 30 minutes on a mini-computer. Unlike other synthesis programs, it searches in an extremely large set of possible circuits (over 1,000,000 configurations), and is not restricted to one device technology. To ensure a high rate of success in the designs, it uses mathematically sound search rules instead of heuristic ones, and accurate approximations of the circuit behavior. These features require considerable computational effort, and therefore it is necessary to use a refined search strategy to reduce the time for a design run. This strategy is also described.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129703180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Partial strength ordering applied to symbolic switch-level analysis 部分强度排序应用于符号开关级分析
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205961
E. Verlind, L. Claesen, M. Genoe, F. Proesmans, H. de Man
{"title":"Partial strength ordering applied to symbolic switch-level analysis","authors":"E. Verlind, L. Claesen, M. Genoe, F. Proesmans, H. de Man","doi":"10.1109/EDAC.1992.205961","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205961","url":null,"abstract":"Presents the application of partially ordered strength sets within the symbolic switch-level analysis of digital MOS circuits, where until now only a straightforward approach using a total ordering was used. The paper gives a mathematical formulation for the analysis. The method has been implemented within the existing switch-level analyzer ANAMOS, and has been applied successfully to practical circuits.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128163984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Planning strategies for area routing 区域路由规划策略
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205950
Chia-Chun Tsai, Sao-Jie Chen, Yuh-Lin Chen, Yu-Hen Hu
{"title":"Planning strategies for area routing","authors":"Chia-Chun Tsai, Sao-Jie Chen, Yuh-Lin Chen, Yu-Hen Hu","doi":"10.1109/EDAC.1992.205950","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205950","url":null,"abstract":"The area routing problem, solved with two meta-planning strategies (graceful retreat and least impact), is presented in this paper. These strategies are used to effectively manage the selection of net segments and the assignment of track resources. Many examples extracted from the literature are experimentally tested and most of layout results are better than other routers.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"483 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130619344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A data flow graph exchange standard 数据流图交换标准
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205921
J. V. Eijndhoven, L. Stok
{"title":"A data flow graph exchange standard","authors":"J. V. Eijndhoven, L. Stok","doi":"10.1109/EDAC.1992.205921","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205921","url":null,"abstract":"Presents a data flow graph exchange standard, agreed upon and used by the partners in the ESPRIT research project, ASCIS. These data flow graphs are generated from known user interface languages such as Silage, VHDL, and C, and are used to drive architectural synthesis packages and formal verification. The graph semantics are defined to offer a unique degree of freedom for time and area optimizations in synthesis, by giving a maximal parallel representation and combining control and data flow in a consistent way. The graph textual exchange format was developed to allow site and application dependent extensions, without disturbing tools who do not know about these.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130899619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
Can supply current monitoring be applied to the testing of analogue as well as digital portions of mixed ASICs? 供电电流监测是否可以应用于混合asic的模拟和数字部分的测试?
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205994
D. A. Camplin, I. Bell, G. Taylor, B. Bannister
{"title":"Can supply current monitoring be applied to the testing of analogue as well as digital portions of mixed ASICs?","authors":"D. A. Camplin, I. Bell, G. Taylor, B. Bannister","doi":"10.1109/EDAC.1992.205994","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205994","url":null,"abstract":"Investigations are made into the suitability of supply current monitoring as a technique for the testing of analogue circuit modules. Iddq monitoring is already recognised in the digital field. The possibility of a unified testing approach for mixed ASICs is raised. The potential effectiveness of the method is investigated. Simulation results are reported to illustrate typical supply current levels for nominal and defective circuits. Analogue fault detection by this technique is compared with detection by observation of the circuit's output.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133079388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Improved port assignment on channel boundaries 改进了信道边界上的端口分配
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205949
E. Levin
{"title":"Improved port assignment on channel boundaries","authors":"E. Levin","doi":"10.1109/EDAC.1992.205949","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205949","url":null,"abstract":"Deals with the task of assigning the crossing of nets on channel boundaries in the layout integration of macro cells. The author's approach to this problem targets both global criteria (overall area, net lengths) and local criteria (improved channel routability). This is done in a two-stage algorithm. In the first stage, all global needs are captured. In the second, all conflicting needs are resolved while taking the specific channel and channel router needs into account. The algorithm is part of Laysys, a layout integration system which was used for the design of the Swordfish ULSI microprocessor.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134473238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信