{"title":"数字电路的功能抽象与形式化证明","authors":"P. Deverchère, J. Madre, J. Guignet, M. Currat","doi":"10.1109/EDAC.1992.205976","DOIUrl":null,"url":null,"abstract":"A discussion is given on the set of tools that has been developed at Bull for functional verification of VLSI circuits. The functional verification process is based on two key concepts. The first one is functional abstraction which consists of automatically producing a functional view of a circuit from a lower level of description that can be either a structural or a layout description. The second one is formal verification that consists of automatically proving that the abstracted view of a circuit is correct with respect to its functional specification given by the circuit designer. The set of tools implementing these concepts is intensively used at Bull by all VLSI circuit designers.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Functional abstraction and formal proof of digital circuits\",\"authors\":\"P. Deverchère, J. Madre, J. Guignet, M. Currat\",\"doi\":\"10.1109/EDAC.1992.205976\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A discussion is given on the set of tools that has been developed at Bull for functional verification of VLSI circuits. The functional verification process is based on two key concepts. The first one is functional abstraction which consists of automatically producing a functional view of a circuit from a lower level of description that can be either a structural or a layout description. The second one is formal verification that consists of automatically proving that the abstracted view of a circuit is correct with respect to its functional specification given by the circuit designer. The set of tools implementing these concepts is intensively used at Bull by all VLSI circuit designers.<<ETX>>\",\"PeriodicalId\":285019,\"journal\":{\"name\":\"[1992] Proceedings The European Conference on Design Automation\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-03-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1992] Proceedings The European Conference on Design Automation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAC.1992.205976\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1992] Proceedings The European Conference on Design Automation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAC.1992.205976","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Functional abstraction and formal proof of digital circuits
A discussion is given on the set of tools that has been developed at Bull for functional verification of VLSI circuits. The functional verification process is based on two key concepts. The first one is functional abstraction which consists of automatically producing a functional view of a circuit from a lower level of description that can be either a structural or a layout description. The second one is formal verification that consists of automatically proving that the abstracted view of a circuit is correct with respect to its functional specification given by the circuit designer. The set of tools implementing these concepts is intensively used at Bull by all VLSI circuit designers.<>
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