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[1992] Proceedings The European Conference on Design Automation最新文献

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DaDaMo-a conceptual data model for electronic design applications dadamo -电子设计应用的概念数据模型
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205963
W. Heijenga, U. Jasnoch, E. Radeke
{"title":"DaDaMo-a conceptual data model for electronic design applications","authors":"W. Heijenga, U. Jasnoch, E. Radeke","doi":"10.1109/EDAC.1992.205963","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205963","url":null,"abstract":"DaDaMo is a conceptual data model for design applications requiring complex modelling techniques. By the integration and extension of semantic and object-oriented modelling concepts, DaDaMo provides modelling mechanisms considering especially the requirements of complex design applications. These mechanisms are described in detail and their adequacy in particular for electronic design applications is shown. Additionally, experiences in using DaDaMo and the consideration of international standardization efforts are reported.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"13 15","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132748641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A pragmatic approach to the automation of the logic design process 逻辑设计过程自动化的实用方法
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205935
H.N. Nguyen, L. Ducousso, M. Thill, P. Vallet
{"title":"A pragmatic approach to the automation of the logic design process","authors":"H.N. Nguyen, L. Ducousso, M. Thill, P. Vallet","doi":"10.1109/EDAC.1992.205935","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205935","url":null,"abstract":"The paper describes a logic-design system and its associated methodology used in developing the BULL DPS7000 mainframe system. The originality of the work lies in the methodology that integrates a set of state-of-the-art logic synthesis and formal verification techniques to make an effective logic-design system to support an iterative synthesis process.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114786652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Incremental meta-data construction for VLSI design databases VLSI设计数据库的增量元数据构建
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205964
T. Chiueh, R. Katz
{"title":"Incremental meta-data construction for VLSI design databases","authors":"T. Chiueh, R. Katz","doi":"10.1109/EDAC.1992.205964","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205964","url":null,"abstract":"VLSI design databases are typically based on object-oriented data models, which provide primitives for modeling and manipulating design objects and their inter-relationships. However, in practice it is rather difficult for end users (i.e. circuit designers) to understand these primitives, let alone interact with them directly. Unfortunately, existing systems assume that it is the user's responsibility to explicitly build up the meta-data, by which is meant attribute and relationship information. This paper presents a novel incremental meta-data construction paradigm, which is based on (1) a structured design history model, and (2) the specifications of tool-specific execution semantics. Using this paradigm, the authors design and implement algorithms that automatically establish per-object attributes and inter-object relationships as a side effect of CAD tool execution. Consequently the rich modeling capability of an object-oriented database can be fully exploited in a design environment without circuit designers' participation in meta-data construction.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116854767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Solving the path sensitization problem in linear time 求解线性时间内的路径敏化问题
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205959
P. Altenbernd, J. Strathaus
{"title":"Solving the path sensitization problem in linear time","authors":"P. Altenbernd, J. Strathaus","doi":"10.1109/EDAC.1992.205959","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205959","url":null,"abstract":"Presents a new algorithm which computes in linear time with respect to the size of the circuit if a given path is sensitizable or not. The algorithm is based on a set of sensitizing conditions. Besides handling feedback loops, the algorithm works hierarchically, and considers the delay of each circuit element (dynamic sensitization). The trade-off made to gain a linear runtime behavior is discussed. The algorithm is implemented as a component of an interactive timing verifier.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121662911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Parallel sequence fault simulation for synchronous sequential circuits 同步顺序电路并联顺序故障仿真
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205971
Chen-Pin Kung, Chen-Shang Lin
{"title":"Parallel sequence fault simulation for synchronous sequential circuits","authors":"Chen-Pin Kung, Chen-Shang Lin","doi":"10.1109/EDAC.1992.205971","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205971","url":null,"abstract":"A novel parallel sequence fault simulation (PSF) algorithm for synchronous sequential circuits is presented. The algorithm partitions a given test sequence into subsequences of equal length and then performs fault simulation with these subsequences in parallel. To overcome the state dependency of sequential circuits, a multiple-pass method is developed to use minimal simulation passes. The experimental results of PSF on the benchmark circuits show that the speedup ratio over a serial sequence fault simulator is 6.6 on average for random test sequences.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121762812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Testing analog circuits by sensitivity computation 用灵敏度计算测试模拟电路
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205993
M. Slamani, B. Kaminska
{"title":"Testing analog circuits by sensitivity computation","authors":"M. Slamani, B. Kaminska","doi":"10.1109/EDAC.1992.205993","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205993","url":null,"abstract":"An approach is presented for fault diagnosis, at component level of analog circuits, by using functional testing. It is based on the determination of the deviation of one or many components with respect to the value fixed by the designer. Components deviation is determined by measuring a number of output parameters and by sensitivity estimation. A solution of the test equations, based on the sensitivity matrix, gives the deviation of the defective components. Different types of measurements are combined to achieve an adequate test coverage with a minimum cost. Some experimental results are given to clarify the approach and to show its efficiency.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123234928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Generating prime and irredundant covers for binary decision diagrams 生成二元决策图的素数和无冗余盖
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205903
R.P. Jacobi, A. Trullemans
{"title":"Generating prime and irredundant covers for binary decision diagrams","authors":"R.P. Jacobi, A. Trullemans","doi":"10.1109/EDAC.1992.205903","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205903","url":null,"abstract":"The paper presents algorithms for two-level logic minimization of Boolean functions represented by Modified Binary Decision Diagrams (MBDs). MBDs allow the representation of the don't care set in the same graph. The main goal is to produce prime and irredundant covers for these MBDs. A new kind of mixed two-level representation is adopted, where each cube is itself a MBD. Results obtained are comparable to those from ESPRESSO.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128480490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Heuristics for computing robust tests for stuck-open faults from stuck-at test sets 从卡住测试集计算卡住打开故障的鲁棒性测试的启发式方法
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205968
S. Chakravarty
{"title":"Heuristics for computing robust tests for stuck-open faults from stuck-at test sets","authors":"S. Chakravarty","doi":"10.1109/EDAC.1992.205968","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205968","url":null,"abstract":"Heuristics for identifying stuck-open faults for which a robust test can be computed from any stuck-at-test set are presented. Experimental results show that these heuristics can be used to compute robust tests for a large percentage of stuck-upon faults. Since stuck-at test generation is considerably faster than computing a robust test-pair for a given stuck-open fault, these heuristics can be used to speed up the process of computing robust tests for stuck-open faults. The author addresses the problem of computing robust tests for stuck-open faults in static CMOS circuits consisting of NOT, NAND, NOR, AND and OR gates.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130227419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Controlling cooperation through design-object specification-a database-oriented approach 通过设计对象规范控制合作——一种面向数据库的方法
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205887
C. Hubel, W. Kafer, B. Sutter
{"title":"Controlling cooperation through design-object specification-a database-oriented approach","authors":"C. Hubel, W. Kafer, B. Sutter","doi":"10.1109/EDAC.1992.205887","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205887","url":null,"abstract":"The authors propose an operational framework for supporting cooperative design processes carried out by a group of designers. Besides the cooperative refinement of the design-object specification, the introduced cooperation protocol allows cooperative design by system-controlled interchange of design object versions. The versions reflect the process of step-wise improving the design object so as to meet finally its specification. The authors introduce a data integrated design environment based on a nonstandard database system in order to manage the whole cooperation process, i.e. the design objects, the versions, and the design activities.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125534473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Verification of self-checking properties by means of output code space computation 用输出码空间计算的方法验证自检特性
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205916
M. Nicolaidis, M. Boudjit
{"title":"Verification of self-checking properties by means of output code space computation","authors":"M. Nicolaidis, M. Boudjit","doi":"10.1109/EDAC.1992.205916","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205916","url":null,"abstract":"In complex self-checking systems several blocks (i.e. functional blocks and checkers) are embedded. In order to check the self-checking properties of such blocks one needs to know the set of vectors they receive from the blocks feeding their inputs (i.e. the code word output spaces of the source blocks). In a complex system the computation of the output spaces by means of exhaustive simulation of the system is intractable. The paper presents a tool which performs this computation with low CPU time. This tool is a part of PROTECT, a tool which is aimed at automatic generation of complex self-checking circuits.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"520 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123067024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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