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[1992] Proceedings The European Conference on Design Automation最新文献

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A realization algorithm of asynchronous circuits from STG 一种基于STG的异步电路实现算法
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205946
Kuan-Jen Lin, Chen-Shang Lin
{"title":"A realization algorithm of asynchronous circuits from STG","authors":"Kuan-Jen Lin, Chen-Shang Lin","doi":"10.1109/EDAC.1992.205946","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205946","url":null,"abstract":"The synthesis of asynchronous circuits from the behavioral descriptions in signal transition graphs (STG) is studied. A new realization algorithm is proposed to synthesize asynchronous circuits directly from STGs and thereby to maintain the problem size proportional to the signal number only. In previous methods, the state diagram was involved in the synthesis, which has a worst-case size exponential to the signal number. Based on the transitive lock relation, the authors' realization algorithm is shown to realize a one-level circuit when the given STG is L/sup t2/. The simple one-level realization ensures that the realized circuit is hazard-free under the gate delay model without any post-realization modification.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122313123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Input driven synthesis of PLDs and PGAs 输入驱动的pld和pga合成
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205891
B. Babba, M. Crastes, G. Saucier
{"title":"Input driven synthesis of PLDs and PGAs","authors":"B. Babba, M. Crastes, G. Saucier","doi":"10.1109/EDAC.1992.205891","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205891","url":null,"abstract":"The paper presents a fast and efficient algorithm for synthesis of Boolean functions on Xilinx and PAL devices. It starts from lexicographical factorized trees and performs a partitioning of these aces defined by 'input slices'. This allows the creation of subfunctions depending on identical subsets of inputs which can then be easily clustered into the same physical device. Results are shown for a large set of benchmarks and compared with the best existing results available both in terms of the number of devices and the depth related to the critical path.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129497538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Automatic generation of a single-chip solution for board-level BIST of boundary scan boards 边界扫描板的板级BIST的单片自动生成解决方案
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205913
J. Ferreira, J. S. Matos, F. S. Pinto
{"title":"Automatic generation of a single-chip solution for board-level BIST of boundary scan boards","authors":"J. Ferreira, J. S. Matos, F. S. Pinto","doi":"10.1109/EDAC.1992.205913","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205913","url":null,"abstract":"The automatic generation of a hierarchical self-test architecture for boards with boundary scan test (BST) is described, based on a test processor specifically designed to implement the basic operations required to control the BST infrastructure. An ATPG module generates the ROM containing the test program, allowing a single-chip self-test solution with minimal design-for-testability overhead. The same test processor may be used without internal ROM, when a single-chip solution is not desirable.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128438883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A synthesis for testability technique for PLA-based finite state machines 基于pla的有限状态机可测试性技术的综合
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205955
S. Chakradhar, S. Kanjilal, V. Agrawal
{"title":"A synthesis for testability technique for PLA-based finite state machines","authors":"S. Chakradhar, S. Kanjilal, V. Agrawal","doi":"10.1109/EDAC.1992.205955","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205955","url":null,"abstract":"Proposes a method of testable synthesis in which a test function is incorporated into the state diagram of the object machine. The authors constrain logic minimization such that a fault has predictable effect on the composite machine (object machine embedded with the test function). This allows effective use of the test function, even when both object and test machines are faulty. A valid test sequence for a crosspoint fault is obtained by augmenting the combinational test with pre-designed O(log/sub 2/ n) initialization and propagation sequences. Experimental results on the Synthesis benchmark set are given.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127006725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Data configuration in an object oriented persistent programming environment for CAD 面向对象的CAD持久化编程环境中的数据配置
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205965
M. Sim, P. M. Kist, C. Schot
{"title":"Data configuration in an object oriented persistent programming environment for CAD","authors":"M. Sim, P. M. Kist, C. Schot","doi":"10.1109/EDAC.1992.205965","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205965","url":null,"abstract":"Evaluates a methodology based on the object-oriented and persistent paradigms for the interfacing of CAD tools with a framework with emphasis on rapid prototyping. This combination ensures that all objects (design data) may be manipulated in a uniform manner, are virtual and possess object-oriented characteristics, be they of a volatile or persistent nature. In such a methodology, configuration is necessary to regulate the persistent aspects of the data. The authors discuss the configuration requirements, the problems and the solutions as realized in a software system named OPI. In OPI, a recursive clustering strategy enables maximum flexibility of persistent data configuration. The user (tool programmer) may select the data that is to persist and control where and how it should be stored. Unique in this approach is that the system employs partitioning algorithms that enable it to work with a minimal set of configuration data. Additional data may be entered piece-meal, resulting in better run-time performance, or more accurate partitioning.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"39 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121011339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Table models for efficient MOS circuit simulation on vector processors 矢量处理器上高效MOS电路仿真的表模型
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205925
K. M. Eickhoff
{"title":"Table models for efficient MOS circuit simulation on vector processors","authors":"K. M. Eickhoff","doi":"10.1109/EDAC.1992.205925","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205925","url":null,"abstract":"A new circuit simulator for the accurate and economical analysis of large MOS circuits is presented. The use of table models instead of analytical models improves the classical circuit simulation in two aspects: First, the generation of the underlying data tables from numerical device simulations enhances the accuracy and enables the evaluation of future technologies. Secondly, the much higher vectorizability results in a simulation speed-up of up to 25 on vector processors.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"440 7087 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124274968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Signature analysis under a delay fault model 时延故障模型下的特征分析
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205940
J. Saxena, D. Pradhan
{"title":"Signature analysis under a delay fault model","authors":"J. Saxena, D. Pradhan","doi":"10.1109/EDAC.1992.205940","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205940","url":null,"abstract":"A framework for aliasing under a delay fault model is presented. First, error patterns under this fault model are characterized. Through this, specific error patterns that can occur are identified. Based on this, it is shown that using a model similar to the equiprobable model, the aliasing probability under certain conditions converges to 2/sup -m/ for delay faults as well. A closed form expression for aliasing under an independent error model is also derived. This expression is shown to yield better theoretical estimates of the aliasing probability.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124511351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Variable ordering for binary decision diagrams 二元决策图的变量排序
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205974
S.-W. Jeong, B. Plessier, G. Hachtel, F. Somenzi
{"title":"Variable ordering for binary decision diagrams","authors":"S.-W. Jeong, B. Plessier, G. Hachtel, F. Somenzi","doi":"10.1109/EDAC.1992.205974","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205974","url":null,"abstract":"Considers the problem of variable ordering in binary decision diagrams (BDD's). The authors present several heuristics for finding a good variable ordering based on the algebraic structure of the functions. They provide a non-interleaving theorem and an accurate cost formula for the optimal ordering. They treat the output ordering problem when a given circuit has multiple outputs and propose new heuristics for the problem and experimental results which enables a quick comparison of some existing heuristics and the proposed heuristics.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121663551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Functional testing of modern microprocessors 现代微处理器的功能测试
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205953
T.J.W. Verhallen, A. van de Goor
{"title":"Functional testing of modern microprocessors","authors":"T.J.W. Verhallen, A. van de Goor","doi":"10.1109/EDAC.1992.205953","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205953","url":null,"abstract":"In the early 1980s, a method was developed for functional testing of microprocessors. Modern microprocessors have a functionality, such as on-chip caches, which is not covered by that model. This paper extends that functional model and proposes fault models, together with tests for such modern microprocessors. The proposed concepts and algorithms have been applied to the Intel i860 microprocessor chip.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122054687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design automation of power integrated circuits in EDGE environment EDGE环境下电源集成电路的自动化设计
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205933
L. Hébrard, G. Jacquemod, B. Boutherin, M. Le Helley
{"title":"Design automation of power integrated circuits in EDGE environment","authors":"L. Hébrard, G. Jacquemod, B. Boutherin, M. Le Helley","doi":"10.1109/EDAC.1992.205933","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205933","url":null,"abstract":"Presents SETIPIC, a software package to forecast the electrothermal interactions in the first design steps of power integrated circuits. To give a well-consistent interface with graphic tools to the designer, SETIPIC works under the EDGE CAD system. The software aspect of this integration into EDGE is explained. PICMOST, the thermal simulator used by SETIPIC to obtain the thermal distribution on the layout surface in a transient or stationary mode is also described. In particular, the method to take into account the chip environment (package...) with an automatic mesh to handle aleatory layout configurations is explained. Finally, some thermal simulation results are given.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123470482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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