A synthesis for testability technique for PLA-based finite state machines

Abstract

Proposes a method of testable synthesis in which a test function is incorporated into the state diagram of the object machine. The authors constrain logic minimization such that a fault has predictable effect on the composite machine (object machine embedded with the test function). This allows effective use of the test function, even when both object and test machines are faulty. A valid test sequence for a crosspoint fault is obtained by augmenting the combinational test with pre-designed O(log/sub 2/ n) initialization and propagation sequences. Experimental results on the Synthesis benchmark set are given.<>