Table models for efficient MOS circuit simulation on vector processors

Abstract

A new circuit simulator for the accurate and economical analysis of large MOS circuits is presented. The use of table models instead of analytical models improves the classical circuit simulation in two aspects: First, the generation of the underlying data tables from numerical device simulations enhances the accuracy and enables the evaluation of future technologies. Secondly, the much higher vectorizability results in a simulation speed-up of up to 25 on vector processors.<>