Hardware selection and clustering in the HYPER synthesis system

Abstract

A novel approach for the hardware selection and clustering problem in high level synthesis is presented. The goal of the hardware selection is to select a set of hardware modules which minimize the implementation cost of an algorithm, given the timing and throughput constraints. At the same time, simple operators are clustered into large combinatorial blocks to reduce the register count and to increase the throughput. The proposed approach is organized as a search employing a relaxed scheduling for cost estimation and uses a simple, yet accurate timing analysis to verify timing constraints. The results from real applications showed the excellent performance of the proposed algorithm.<>