Synthesis and optimization of synchronous logic circuits from recurrence equations

Abstract

The paper presents a general solution framework for optimizing synchronous networks across register boundaries. It formulates the problem as that of finding minimum-cost solutions to synchronous recurrence equations. It proposes an algorithm for the solution of such equations that relies on their transformation into a new combinational logic optimization problem. An exact solution algorithm for this problem is presented, and experimental results on synchronous benchmark circuits demonstrate the feasibility of the approach.<>