Automatic formal verification of Cathedral-II circuits from transistor switch level implementation up to high level behavioral specifications by the SFG-tracing methodology

Abstract

Research on the verification of synchronous circuits has been focussed recently on alternative methodologies instead of traditional methods like ad-hoc simulation. Where logic simulation can not avoid the combinatorial explosion that would normally occur when evaluating circuits for each possible input and initial state, new methods such as theorem proving, tautology checking and symbolic simulation are challenges to a more straightforward approach of fully correct circuit design. A new methodology called SFG-Tracing has been developed. It makes use of the concept of ordered binary decision diagrams (OBDDs). This general methodology is currently applied for the automatic verification of the results of the Cathedral Silicon Compilers. For the Cathedral-II system a complete verification environment has been built that allows to verify circuits from transistor switch level up to their high level algorithmic specifications.<>