The effect of multiple charge-discharge paths on testing of BiCMOS logic circuits

Abstract

Due to the presence of multiple paths to charge or discharge the output node of a BiCMOS logic gate, many of the realistic open and short faults appear as rise or fall time delay faults without changing the functionality of the circuit. Based on circuit level faults, it has been observed that delay fault tests can produce a fault coverage as high as 92% compared to 29% produced by stuck-at tests, for the same set of faults for a BiCMOS inverter. The implications of this dominant failure mode are discussed and a gate level design-for-testability (DFT) scheme is presented.<>