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[1992] Proceedings The European Conference on Design Automation最新文献

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An asynchronous architecture model for behavioral synthesis 用于行为综合的异步体系结构模型
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205944
J. Cortadella, R. Badia
{"title":"An asynchronous architecture model for behavioral synthesis","authors":"J. Cortadella, R. Badia","doi":"10.1109/EDAC.1992.205944","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205944","url":null,"abstract":"An asynchronous architecture model for behavioral synthesis is presented. The basis of the model lies in a distributed control structure consisting of multiple communicating processes. Data processing is performed by self-timed modules. Signal transition graphs (STGs) are used to specify the behavior of the control processes. By using existing synthesis procedures for STGs, circuits based on the presented architecture model are proved to be realizable and hazard-free.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122381274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Parametric ASIC-design by CADIC 基于CADIC的参数化asic设计
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205936
R. Drefenstadt
{"title":"Parametric ASIC-design by CADIC","authors":"R. Drefenstadt","doi":"10.1109/EDAC.1992.205936","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205936","url":null,"abstract":"Large ASIC's often include regular blocks such as memories, arithmetic units and random logic. The design system CADIC enables a comfortable description of small and large blocks by a graphic interface. The paper describes experiences in the design of an ASIC chip implementing an efficiently testable floating point adder. By help of this example it is shown that CADIC combines both kinds of logic. Also it is possible to optimize the propagation delay of the floating point adder using specially adapted subcircuits.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128876267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Timing verification: a new understanding of false paths 定时验证:对错误路径的新理解
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205960
E. Bolender, Martin Lipp
{"title":"Timing verification: a new understanding of false paths","authors":"E. Bolender, Martin Lipp","doi":"10.1109/EDAC.1992.205960","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205960","url":null,"abstract":"Despite the growing number of timing verification algorithms, a concise formal approach for the definition of false paths is missing. In this paper, based on the logical and delay properties of the discussed circuits, some precise formal definitions are derived with two major advantages. First, they make the understanding of false paths surprisingly intelligible. Second, they are independent of algorithmic interpretations because of their formal derivation.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129835244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Scheduling between basic blocks in the CADDY synthesis system CADDY合成系统中基本模块之间的调度
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205985
P. Gutberlet, W. Rosenstiel
{"title":"Scheduling between basic blocks in the CADDY synthesis system","authors":"P. Gutberlet, W. Rosenstiel","doi":"10.1109/EDAC.1992.205985","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205985","url":null,"abstract":"In 'high level' IC synthesis, basic blocks are caused by the control schemes and the block structure of the specification language (branches, loops). These schemes must be considered by the construction of the controller. A method is presented to handle the basic blocks in a more flexible way which allows one to move operations between basic block boundaries. The goal is to improve the number of control steps of the circuit under fixed hardware resources.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124515934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Automatic synthesis of large Moore sequencers 自动合成大型摩尔测序仪
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205930
L. Gerbaux, G. Saucier
{"title":"Automatic synthesis of large Moore sequencers","authors":"L. Gerbaux, G. Saucier","doi":"10.1109/EDAC.1992.205930","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205930","url":null,"abstract":"The automatic synthesis of large Moore sequencers is performed on architectures whose novel features include the use of a ROM, a partitioned micro-sequencer on standard cells and a masking technique which restricts the computation of next state codes to significant bits. Extensive experiments have shown the efficiency of the approach in terms of both area and speed compared with a full standard cell implementation.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"75 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130968442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A parallel hierarchical design rule checker 并行分层设计规则检查器
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205910
N. Hedenstierna, K.O. Jeppson
{"title":"A parallel hierarchical design rule checker","authors":"N. Hedenstierna, K.O. Jeppson","doi":"10.1109/EDAC.1992.205910","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205910","url":null,"abstract":"The halo algorithm, a novel and efficient algorithm for hierarchical design-rule checking (DRC) has been modified for parallel processing. Like the sequential halo algorithm, the parallel version identifies repeated subcell interactions and checks them only once thereby improving performance substantially. Inverse layout trees are used to handle interacting primitives hierarchically. The algorithm has been implemented on workstations connected by a local area network and on a shared memory multicomputer.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126732239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Resources restricted aggressive scheduling 资源受限主动调度
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205986
P. Yeung, D. J. Rees
{"title":"Resources restricted aggressive scheduling","authors":"P. Yeung, D. J. Rees","doi":"10.1109/EDAC.1992.205986","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205986","url":null,"abstract":"A scheduling methodology is described for high-level synthesis of designs with a significant amount of control structure. The objective is to utilize all the available resources while scheduling with respect to resource restriction. To do so, a vector/matrix structure is built which provides a global view of resource usage at each node. It supports the migration of operations across basic blocks to wherever idle resources are available. With it, the authors formulate a list scheduling algorithm in which the dispatching priority changes dynamically with respect to resource availability.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115215361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Global weighted scheduling and allocation algorithms 全局加权调度和分配算法
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205984
H. Oudghiri, B. Kaminska
{"title":"Global weighted scheduling and allocation algorithms","authors":"H. Oudghiri, B. Kaminska","doi":"10.1109/EDAC.1992.205984","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205984","url":null,"abstract":"Scheduling and allocation are very complex problems in a high-level synthesis system. It was proven, in related work, that the two are NP-complete optimization problems. The authors introduce a new global approach for scheduling and allocation. The approach uses graphs to formulate the two problems and applies a partitioning procedure on these graphs to find the minimal number of cliques. The obtained cliques correspond to the time steps in scheduling and to hardware elements required in allocation. The partitioning procedure is made more efficient by weighting the graph edges by the profit to group nodes together. The procedure was programmed in C++ and experimental results are given to show its efficiency to solve both scheduling and allocation.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129649831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Quiescent current estimation for current testing 用于电流测试的静态电流估计
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205995
L. Balado, J. Figueras, J. A. Rubio, V. Champac, R. Rodríguez, J. Segura
{"title":"Quiescent current estimation for current testing","authors":"L. Balado, J. Figueras, J. A. Rubio, V. Champac, R. Rodríguez, J. Segura","doi":"10.1109/EDAC.1992.205995","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205995","url":null,"abstract":"Logic voltage testing has some limitations dealing with defects that turn digital into analog values. For these parametric faults, current testing is being considered as a promising complementary technique. A methodology to characterize the quiescent circuit consumption in a new way that simplifies the electrical simulation of a complex VLSI circuit is proposed. Further it is exemplified on the C17 IS-CAS circuit, concluding that the proposed method has been successful in the example and can be easily programmed to estimate I/sub ddq/ for large circuits without the well known electrical simulation time penalty.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129140718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Verified high-level synthesis in BEDROC 在BEDROC中验证了高水平合成
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205894
R. Chapman, G. Brown, M. Leeser
{"title":"Verified high-level synthesis in BEDROC","authors":"R. Chapman, G. Brown, M. Leeser","doi":"10.1109/EDAC.1992.205894","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205894","url":null,"abstract":"The authors present the HardwarePal hardware description language and formal operational and denotational semantics for it, briefly discussing their proof of the two semantics' equivalence. They then discuss their intermediate representation, dependence flow graphs, and the operational semantics of DFG. They describe the translation from HardwarePal to dependence flow graphs and outline their proof that this translation preserves the meaning of the initial HardwarePal program. The authors discuss proving the correctness of the translation from behavioral specification to intermediate form, proving the correctness of optimizations, and plans for proving the correctness of scheduling. The authors conclude by discussing their plans for proofs that register-transfer level design produced by BEDROC implements the dependence flow graph.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121093738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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