{"title":"定时验证:对错误路径的新理解","authors":"E. Bolender, Martin Lipp","doi":"10.1109/EDAC.1992.205960","DOIUrl":null,"url":null,"abstract":"Despite the growing number of timing verification algorithms, a concise formal approach for the definition of false paths is missing. In this paper, based on the logical and delay properties of the discussed circuits, some precise formal definitions are derived with two major advantages. First, they make the understanding of false paths surprisingly intelligible. Second, they are independent of algorithmic interpretations because of their formal derivation.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Timing verification: a new understanding of false paths\",\"authors\":\"E. Bolender, Martin Lipp\",\"doi\":\"10.1109/EDAC.1992.205960\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Despite the growing number of timing verification algorithms, a concise formal approach for the definition of false paths is missing. In this paper, based on the logical and delay properties of the discussed circuits, some precise formal definitions are derived with two major advantages. First, they make the understanding of false paths surprisingly intelligible. Second, they are independent of algorithmic interpretations because of their formal derivation.<<ETX>>\",\"PeriodicalId\":285019,\"journal\":{\"name\":\"[1992] Proceedings The European Conference on Design Automation\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-03-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1992] Proceedings The European Conference on Design Automation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAC.1992.205960\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1992] Proceedings The European Conference on Design Automation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAC.1992.205960","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Timing verification: a new understanding of false paths
Despite the growing number of timing verification algorithms, a concise formal approach for the definition of false paths is missing. In this paper, based on the logical and delay properties of the discussed circuits, some precise formal definitions are derived with two major advantages. First, they make the understanding of false paths surprisingly intelligible. Second, they are independent of algorithmic interpretations because of their formal derivation.<>