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[1992] Proceedings The European Conference on Design Automation最新文献

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The Sprite Input Language-an intermediate format for high level synthesis 精灵输入语言——用于高级合成的中间格式
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205920
T. Krol, J. van Meerbergen, C. Niessen, W. Smits, J. Huisken
{"title":"The Sprite Input Language-an intermediate format for high level synthesis","authors":"T. Krol, J. van Meerbergen, C. Niessen, W. Smits, J. Huisken","doi":"10.1109/EDAC.1992.205920","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205920","url":null,"abstract":"Describes a simple and powerful input language (intermediate format) for high level synthesis. The language belongs to the class of signalflow graphs. The Sprite Input Language (SIL) encompasses both the applicative constructs on which classical DSP languages like Silage are based, the functional constructs from hardware description languages like ELLA, and the operational constructs from sequential languages like Pascal and C. This is obtained by means of the single token flow model and using sets instead of single values for data modelling. The language is suited for acting as an intermediate language between the various specification languages and the silicon compilation system, as well as a language backbone in the synthesis part of a silicon compiler.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121285173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Multicell quad trees 多细胞四棱树
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205911
S. Su, Y.S. Kuo
{"title":"Multicell quad trees","authors":"S. Su, Y.S. Kuo","doi":"10.1109/EDAC.1992.205911","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205911","url":null,"abstract":"The multicell quad tree is a two-level tree structure for region queries. At the upper level is a multiple storage quad tree (MSQT). At the lower level, each leaf quad of the MSQT is further subdivided into equal-sized cells. Basically, large-window queries examine structures at the coarse-grained leaf quad level while small-window queries examine structures at the fine-grained cell level. With such two-level structures fitting each kind of queries separately, both large-window and small-window queries can achieve high execution speeds.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125494809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An alternative to fault simulation for delay-fault diagnosis 延迟故障诊断的故障模拟替代方案
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205938
P. Girard, C. Landrault, S. Pravossoudovitch
{"title":"An alternative to fault simulation for delay-fault diagnosis","authors":"P. Girard, C. Landrault, S. Pravossoudovitch","doi":"10.1109/EDAC.1992.205938","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205938","url":null,"abstract":"Delay testing is a test procedure to verify the timing performance of manufactured digital circuits. A diagnosis process is often implemented after the detection of a fault in a circuit. Unfortunately, existing methodologies for locating delay defects on digital circuits have shown certain deficiencies. A new method for delay fault diagnosis, based on critical path tracing from a symbolic simulation, is presented. This method needs to consider only the fault-free circuit and provides perfectly reliable results. It does not require timing evaluations and can be very accurate.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133475564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Testing embedded single and multi-port RAMs using BIST and boundary scan 测试嵌入式单和多端口ram使用BIST和边界扫描
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205914
V. Castro Alves, M. Lubaszewski, M. Nicolaidis, B. Courtois
{"title":"Testing embedded single and multi-port RAMs using BIST and boundary scan","authors":"V. Castro Alves, M. Lubaszewski, M. Nicolaidis, B. Courtois","doi":"10.1109/EDAC.1992.205914","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205914","url":null,"abstract":"The paper presents a general BIST scheme for the test of RAMs (single and multi-port) embedded in very complex ASICs. A simple BIST circuit driven by the IEEE standard for the boundary scan (BS) is shared by all the memories that are tested simultaneously. The area overhead is greatly compensated by the test development time reduction and the link with BS.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134367153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multilevel logic synthesis based on functional decision diagrams 基于功能决策图的多级逻辑综合
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205890
U. Kebschull, E. Schubert, W. Rosenstiel
{"title":"Multilevel logic synthesis based on functional decision diagrams","authors":"U. Kebschull, E. Schubert, W. Rosenstiel","doi":"10.1109/EDAC.1992.205890","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205890","url":null,"abstract":"The authors introduce an efficient data structure for Boolean function representation and present a new algorithm for the synthesis of multilevel logic. Other algorithms represent Boolean functions in the operational domain using Sum-of-Products representations. The authors prefer the synthesis in the functional domain using the less complex Reed-Muller Expansion. The algorithm bases on a new efficient representation, the so-called functional decision diagrams, which are herewith presented. The authors implemented this algorithm, the results are encouraging.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131604654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 225
Advanced ordering and manipulation techniques for binary decision diagrams 二元决策图的高级排序和操作技术
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205975
N. Calazans, Qinhai Zhang, R. Jacobi, B. Yernaux, A. Trullemans
{"title":"Advanced ordering and manipulation techniques for binary decision diagrams","authors":"N. Calazans, Qinhai Zhang, R. Jacobi, B. Yernaux, A. Trullemans","doi":"10.1109/EDAC.1992.205975","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205975","url":null,"abstract":"Heuristics leading to improved ordering computation for binary decision diagrams (BDDs) are given. An initial step, based on the topology of the network, generates a hierarchical variable ordering. This initial result is further refined by incremental manipulation governed by the stochastic evolution technique. A new property of BDDs is introduced as well, which accelerates commonly used operations. Experimental results are presented. Binary decision diagrams (BDDs) have been known for a long time as a means to represent the structure of switching functions, but only recently their use emerged in the implementation of design automation tools for digital circuits.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115708444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Combined scheduling and data routing for programmable ASIC systems 可编程ASIC系统的组合调度和数据路由
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205983
R. Hartmann
{"title":"Combined scheduling and data routing for programmable ASIC systems","authors":"R. Hartmann","doi":"10.1109/EDAC.1992.205983","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205983","url":null,"abstract":"A technique for mapping complex signal processing algorithms on programmable ASIC systems is presented. It integrates data routing into scheduling. An important problem is to cope with deadlocks during scheduling caused by limited register resources and fixed interconnect. An algorithm is presented which is able to generate a schedule for a broad class of architectures. It is integrated into a retargetable microcode compiler based on the Cathedral2nd framework. It was tested using an ISDN echo cancelling algorithm.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116441804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
Synthesis of sequential circuits for parallel scan 并行扫描顺序电路的合成
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205956
B. Vinnakota, N. K. Jha
{"title":"Synthesis of sequential circuits for parallel scan","authors":"B. Vinnakota, N. K. Jha","doi":"10.1109/EDAC.1992.205956","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205956","url":null,"abstract":"Sequential circuit testing is known to be a difficult problem. The authors present a synthesis for testability (SFT) method to solve this problem. In this approach, some testability features analogous to the traditional scan design are added to the normal logic equations which define the finite state machine (FSM). The augmented FSM is then synthesized with these added features built in. The overhead may thus be reduced as the logic needed to obtain testability is merged with the logic needed for normal functionality. Another advantage of this approach is that the test set length is usually very small; in many cases, the authors obtain a sequential test which is roughly only twice the size of the combinational test set derived for the combinational logic of the sequential circuit. This drastically reduces the test application time without sacrificing the advantages of scan design: high fault coverage and low test generation time. By applying their method to benchmark FSM examples the authors show that the resultant area overhead is also quite low.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123815642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Parallelism extraction and programme restructuring of VHDL for parallel simulation 并行仿真的VHDL并行提取与程序重构
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205899
B. Vellandi, M. Lightner
{"title":"Parallelism extraction and programme restructuring of VHDL for parallel simulation","authors":"B. Vellandi, M. Lightner","doi":"10.1109/EDAC.1992.205899","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205899","url":null,"abstract":"The authors obtained an overall increase in parallelism during VHDL simulation by decomposing simulation models into smaller computational units to be executed in parallel and by parallelizing the simulation support functions. The authors implementation targeted massively parallel architectures. Simulation experimentation and instrumentation was done on the SIMD Connection Machine.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125134295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An efficient method for decomposition of multiple-output Boolean functions and assigned sequential machines 多输出布尔函数和分配顺序机的有效分解方法
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205905
L. Józwiak, F. Volf
{"title":"An efficient method for decomposition of multiple-output Boolean functions and assigned sequential machines","authors":"L. Józwiak, F. Volf","doi":"10.1109/EDAC.1992.205905","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205905","url":null,"abstract":"Since today's complex digital systems and circuits are difficult to design, optimize, implement and verify, decomposition methods and tools have attracted great interest recently. The objective of the new decomposition method presented in this paper is to implement a complex Boolean function or an assigned sequential machine with a minimal number of constrained building blocks and minimal connections between the blocks. The method aims in solving problems with hard constraints in multiple dimensions for which, to the authors' knowledge, no solution has yet been published. It differs substantially from the methods for solving similar simpler one-dimensional problems. The method is very general and, after some small changes, it can be applied to many other partitioning problems. The experimental results show that the method is very efficient.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128310105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
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