Combined scheduling and data routing for programmable ASIC systems

Abstract

A technique for mapping complex signal processing algorithms on programmable ASIC systems is presented. It integrates data routing into scheduling. An important problem is to cope with deadlocks during scheduling caused by limited register resources and fixed interconnect. An algorithm is presented which is able to generate a schedule for a broad class of architectures. It is integrated into a retargetable microcode compiler based on the Cathedral2nd framework. It was tested using an ISDN echo cancelling algorithm.<>