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[1992] Proceedings The European Conference on Design Automation最新文献

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An efficient method for computing transient response of integrated circuits with lossy transmission lines 含损耗传输线集成电路暂态响应的一种有效计算方法
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205926
S. Chowdhury, J. Barkatullah
{"title":"An efficient method for computing transient response of integrated circuits with lossy transmission lines","authors":"S. Chowdhury, J. Barkatullah","doi":"10.1109/EDAC.1992.205926","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205926","url":null,"abstract":"Computing the transient signals in circuits with lossy transmission lines involves evaluation of convolution integrals at each time step. Each convolution integral requires signals from the initial time up to the current time. The paper presents a technique called the polynomial convolution algorithm that allows evaluation of a convolution integral at the current time step by using the result of convolution at the previous time step. Thus storage and computation time requirements are reduced significantly. Accuracy and speed tradeoffs are presented as well as examples of simulation results.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127218105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Intelligent VLSI design object management 智能VLSI设计对象管理
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205966
T. Chiueh, R. Katz
{"title":"Intelligent VLSI design object management","authors":"T. Chiueh, R. Katz","doi":"10.1109/EDAC.1992.205966","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205966","url":null,"abstract":"Designing a VLSI chip is almost always an iterative process and a group effort. As a result, proliferation of design versions, becomes one of the most important issues in the development of design automation systems. The authors present the design and implementation of a VLSI object management system that supports several novel low-level storage management and access control services not found in previous systems. Among them are differential representation for design versions, integration of related versions, constraint-based synchronization mechanisms, and query/link access facilities for exploring the design versions space. This object system lays a foundation for customizing and implementing high-level version/configuration and concurrency control policies according to site-specific and group-specific needs.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127447909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
System-level synthesis using re-programmable components 使用可重新编程组件的系统级综合
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205881
Rajesh K. Gupta, G. Micheli
{"title":"System-level synthesis using re-programmable components","authors":"Rajesh K. Gupta, G. Micheli","doi":"10.1109/EDAC.1992.205881","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205881","url":null,"abstract":"The authors formulate the synthesis problem of complex behavioral descriptions with performance constraints as a hardware-software co-design problem. The target system architecture consists of a software component as a program running on a re-programmable processor assisted by application-specific hardware components. System synthesis is performed by first partitioning the input system description into hardware and software portions and then by implementing each of them separately. The synthesis of dedicated hardware is then achieved by means of hardware synthesis tools (D.D. Mitchell, D.C.Ku, F. Mailhot, and T. Truong, 'The Olympus Synthesis System for digital design' IEEE Design and Test Magazine, p.37-53, Oct. 1990), while the software component is generated using software compiling techniques. The authors consider the problem of identifying potential hardware and software components of a system described in a high-level modeling language and they present a partitioning procedure. They then describe the results of partitioning a network coprocessor.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127676989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 178
MULTIPAR: behavioral partitioning for synthesizing application-specific multiprocessor architecture MULTIPAR:用于合成特定于应用程序的多处理器体系结构的行为分区
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205883
Yunn-Yen Chen, Y. Hsu, C. King
{"title":"MULTIPAR: behavioral partitioning for synthesizing application-specific multiprocessor architecture","authors":"Yunn-Yen Chen, Y. Hsu, C. King","doi":"10.1109/EDAC.1992.205883","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205883","url":null,"abstract":"The authors present methods for scheduling and partitioning behavioral descriptions in order to synthesize application specific multiprocessor systems. The target application domain is real-time digital signal processing (DSP). In order to meet the real-time constraints, maximizing the system throughput and minimizing the number of communications between processors are important. A model of the target processor and the communication device is defined as a basis for synthesizing the multiprocessor system. The authors use an integer linear programming formulation to solve the partitioning and scheduling problem simultaneously. The optimization complexity of large applications can be reduced by using a simplified formulation and an iterative partitioning heuristic. The work also takes into account of conditional branches, loops, and critical signals.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129606091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
PARAGRAPH: a parallel algorithm for simultaneous placement and routing using hierarchy 段落:一个并行算法，用于同时放置和路由使用层次结构
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205948
Randall J. Brouwer, Prithviraj Banerjee
{"title":"PARAGRAPH: a parallel algorithm for simultaneous placement and routing using hierarchy","authors":"Randall J. Brouwer, Prithviraj Banerjee","doi":"10.1109/EDAC.1992.205948","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205948","url":null,"abstract":"Proposes a new parallel algorithm for combined standard cell placement and routing. The focus in this research has been to develop a hierarchical decomposition scheme so that the subproblems are completely independent of each other and can be evaluated in parallel. The authors' have developed a parallel algorithm such that the solution quality does not degrade with the addition of multiple processors, a common problem encountered by most previously reported parallel placement and routing algorithms. The new parallel algorithm hierarchically integrates a quadrisection cell placement algorithm, a bisection placement algorithm, a global routing algorithm, and a detailed routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which are evaluated in parallel using dynamic task scheduling. Finally, the authors present results of an implementation of their parallel algorithm on a shared memory multiprocessor for several industrial benchmark circuits.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132178537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A new approach for checking the unique state coding property of signal transition graphs 一种检测信号转换图唯一状态编码特性的新方法
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205945
Meng-Lin Yu, P. Subrahmanyam
{"title":"A new approach for checking the unique state coding property of signal transition graphs","authors":"Meng-Lin Yu, P. Subrahmanyam","doi":"10.1109/EDAC.1992.205945","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205945","url":null,"abstract":"A signal transition graph (STG) embodies the causal relationships among signal transitions in a system, and provides a useful starting point for the synthesis of asynchronous circuits. The prevalent synthesis techniques require the input STG to possess the unique state coding (USC) property. This paper describes an algorithm to ascertain whether a given STG has the USC property. The algorithm is path-oriented, and has the advantage of operating directly on the STG rather than a state graph. This approach has the advantage of being easier to visually and intuitively correlate with the STG specification, and therefore suggest ways in which a designer (or tool) may modify the input STG if it does not satisfy the USC property. The technique can also be used to compute the input set of a signal.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127876484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Parallel logic simulation on a distributed memory machine 分布式内存机的并行逻辑仿真
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205898
Y. Matsumoto, K. Taki
{"title":"Parallel logic simulation on a distributed memory machine","authors":"Y. Matsumoto, K. Taki","doi":"10.1109/EDAC.1992.205898","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205898","url":null,"abstract":"The paper reports on an efficient logic simulation system using the Time Warp mechanism, implemented on a large-scale multiprocessor (Multi-PSI). The system includes local message schedulers, an antimessage reduction mechanism and a load distribution scheme to enhance performance. In the authors' experiment, using 64 processors, 50-fold speedup and 100 K events/sec performance was obtained. The paper also reports on an empirical comparison between the Time Warp mechanism and two other mechanisms: a conservative approach and a synchronous approach. The comparison shows that the Time Warp mechanism is the most suitable for large-scale multiprocessors.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127954813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Sizing of analogue circuits for small-signal gains 小信号增益模拟电路的尺寸
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205979
R. Henderson, C. Meixenberger, B. Goffart, J. Jongsma, M. Pierre, M. Degrauwe
{"title":"Sizing of analogue circuits for small-signal gains","authors":"R. Henderson, C. Meixenberger, B. Goffart, J. Jongsma, M. Pierre, M. Degrauwe","doi":"10.1109/EDAC.1992.205979","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205979","url":null,"abstract":"Efficient computational techniques are presented for the sizing of analogue circuits subject to small-signal gain specifications. Particular attention is given to the estimation and control of the effects of device mismatch.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128623283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A clock net routing algorithm for high performance VLSI 一种用于高性能VLSI的时钟网路由算法
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205951
Ting-Hai Chao, Y. Hsu
{"title":"A clock net routing algorithm for high performance VLSI","authors":"Ting-Hai Chao, Y. Hsu","doi":"10.1109/EDAC.1992.205951","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205951","url":null,"abstract":"Presents a new algorithm, called FSTM ('feasible segment tree method'), for the clock net routing of high performance VLSI designs. To avoid the clock skew, FSTM constructs a binary tree such that for each internal vertex of the tree, the cardinality of its sub-trees are balanced and the distances to its children are equal. The authors evaluate their results in terms of wire length and delay time (by the SPICE simulator). Experiments show that the clock net trees routed by FSTM achieve 13% in wire length, 3% in maximum delay and 36% in clock skew improvement over previously published results.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128715360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The impact of abstract data types on the digital system description and simulation environments 抽象数据类型对数字系统描述和仿真环境的影响
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205900
N. E. Mause, P. Wilsey
{"title":"The impact of abstract data types on the digital system description and simulation environments","authors":"N. E. Mause, P. Wilsey","doi":"10.1109/EDAC.1992.205900","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205900","url":null,"abstract":"Over the years, many features of programming languages have been adopted in the design of hardware description languages (HDLs). The incorporation of facilities to support building abstract data types in HDLs is examined. In particular, the use of abstract data types in VHDL is considered in the description and simulation of digital systems. Furthermore, the user-interface of a VHDL simulator is considered and the question 'are the benefits of abstract data types defeated by a primitive simulator user interface?' is asked. Finally, an extended VHDL package is shown that provides the designer with a mechanism for extending the user interface of an interactive simulator.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125592205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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