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[1992] Proceedings The European Conference on Design Automation最新文献

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DAC-A silicon compiler system for high performance DSP ASIC dac -一种用于高性能DSP专用集成电路的硅编译系统
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205934
Y. Hu, J. McCanny, M. Yan
{"title":"DAC-A silicon compiler system for high performance DSP ASIC","authors":"Y. Hu, J. McCanny, M. Yan","doi":"10.1109/EDAC.1992.205934","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205934","url":null,"abstract":"An overview is given of an application-specific silicon compiler system called DAC for the automated design of high performance DSP ASIC chips. This system consists of a number of application-specific silicon compilers and a set of universal utilities for the running and programming of these compilers. It provides an environment to systematically develop application-specific silicon compilers.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117094756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automatic jog insertion for 2D mask compaction: a global optimization perspective 2D掩码压缩的自动慢跑插入:全局优化视角
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205988
J.-L. Martineau, G. Bois, E. Cerny
{"title":"Automatic jog insertion for 2D mask compaction: a global optimization perspective","authors":"J.-L. Martineau, G. Bois, E. Cerny","doi":"10.1109/EDAC.1992.205988","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205988","url":null,"abstract":"A novel approach is presented to global optimization in 2D symbolic layout compaction based on 'branch and bound' optimization, including automatic overconstraint resolution and jog insertion. The main characteristics are: an efficient generation in 2D of a nearly irredundant set of simple X and Y, diagonal and user constraints; incremental event-driven longest path calculation with positive cycle detection and identification simultaneously in the X and Y constraint graphs; jog insertion based on LP information from both graphs; and incremental update of constraints based on local information within the graphs whenever a diagonal constraint is relaxed or a jog is inserted. As both dimensions are processed concurrently from a global perspective, the method shows promising results.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132399485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Logic synthesis for arithmetic circuits using the Reed-Muller representation 用里德-穆勒表示的算术电路的逻辑综合
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205904
J. Saul
{"title":"Logic synthesis for arithmetic circuits using the Reed-Muller representation","authors":"J. Saul","doi":"10.1109/EDAC.1992.205904","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205904","url":null,"abstract":"A procedure for multi-level Reed-Muller minimization has been developed which introduces a Reed-Muller factored form, and uses algebraic algorithms for factorization, decomposition, resubstitution, collapsing, and extraction of common cubes and subexpressions. The procedure has been used to design some arithmetic circuits using a gate library containing a wide range of gates, and the resulting circuits were compared with some designed using MisII. The circuits designed using the Reed-Muller system were over 20 percent smaller and between 25 and 50 percent faster.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134309526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
An error decoder for the Compact Disc player as an example of VLSI programming 光盘播放器的错误解码器，作为VLSI编程的一个例子
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205896
J. Kessels, K. V. Berkel, R. Burgess, M. Roncken, F. Schalij
{"title":"An error decoder for the Compact Disc player as an example of VLSI programming","authors":"J. Kessels, K. V. Berkel, R. Burgess, M. Roncken, F. Schalij","doi":"10.1109/EDAC.1992.205896","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205896","url":null,"abstract":"Using a programming language for VLSI design, called Tangram, they design a fast and simple VLSI circuit for error decoding in the Compact Disc player. The derivation of the design is straightforward and the result is succinctly expressed in less than one page of Tangram text. All design decisions are based merely on algorithmic and architectural considerations. No particular VLSI knowledge is needed and, therefore, the exercise demonstrates that Tangram allows system designers to design VLSI circuits. The exercise also shows that in a VLSI programming language special language constructs are essential to obtain efficient designs.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114669707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Principles of design methodology management for electronic CAD frameworks 电子CAD框架设计方法管理原理
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205886
M. Zanella
{"title":"Principles of design methodology management for electronic CAD frameworks","authors":"M. Zanella","doi":"10.1109/EDAC.1992.205886","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205886","url":null,"abstract":"The author introduces a set of design methodology management (DMM) modeling principles as applied to VLSI design environments consisting of CAD tools that were not purposely developed so as to be included into design flows and then do not conform to any specific procedural interface. In the author's view DMM services have two major goals: to discipline designers' behavior and to automate the run of tool sequences. The foundation of a model that includes a taxonomy of design methodologies and supports their representation, enforcement and automation is described.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"300 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116011604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
IBDDs: an efficient functional representation for digital circuits ibdd:数字电路的有效功能表示
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205973
J. Jain, M. Abadir, J. Bitner, D. Fussell, J. Abraham
{"title":"IBDDs: an efficient functional representation for digital circuits","authors":"J. Jain, M. Abadir, J. Bitner, D. Fussell, J. Abraham","doi":"10.1109/EDAC.1992.205973","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205973","url":null,"abstract":"A central issue in the solution of many computer aided design problems is finding a concise representation for circuit designs and their functional specifications. Ordered binary decision diagrams (OBDDs) have recently emerged as a popular representation for various CAD applications such as design verification, synthesis, testing, modeling and simulation. Unfortunately, there is no efficient OBDD representation for many circuits, even in some cases for circuits which perform such apparently simple functions as multiplication. The authors present a new BDD representation scheme, called indexed BDDs (IBDDs), and show that it allows polynomial representations of functions which provably require exponential space using OBDDs. The key idea in IBDDs is to allow multiple occurrences of the input variables, subject to ordering constraints. The authors give an algorithm for verifying the equivalence of two IBDDs and a heuristic for constructing IBDDs for arbitrary combinational circuits.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121011999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
A parallel switch-level simulator for mixed analog-digital circuit simulation 用于混合模数电路仿真的并行开关级模拟器
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205923
Bengt-Arne Molin, S. Mattisson
{"title":"A parallel switch-level simulator for mixed analog-digital circuit simulation","authors":"Bengt-Arne Molin, S. Mattisson","doi":"10.1109/EDAC.1992.205923","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205923","url":null,"abstract":"Presents a parallel event-driven switch-level simulator intended for medium-grain multicomputers. The chosen parallel algorithm ensures that node voltages are always defined. This avoids problems with undefined node states and makes the simulator suitable for mixed analog-digital simulation. The active devices are modeled as piecewise-constant current sources, which gives high timing accuracy and enables simulation of other circuit technologies than MOS logic. Experimental results from simulation of a CMOS synchronous counter run on parallel workstations are presented.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115403879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
YOR: a yield optimizing routing algorithm by minimizing critical area and vias YOR：通过最小化临界面积和过孔来优化产量的路由算法
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205991
S. Kuo
{"title":"YOR: a yield optimizing routing algorithm by minimizing critical area and vias","authors":"S. Kuo","doi":"10.1109/EDAC.1992.205991","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205991","url":null,"abstract":"The goal of a channel routing algorithm is to route the nets with as few tracks as possible to minimize the chip area and achieve 100 percent connection. However, the manufacturing yield may not reach a satisfactory level if care is not taken to reduce the critical areas which are susceptible to defects. A new channel routing algorithm is presented to deal with this problem. The approach is to systematically eliminate critical areas by floating, burying, and bumping net segments as well as shifting vias. The yield optimizing routing (YOR) algorithm also minimizes the number of vias. The experimental results show that large reduction in the number of critical areas and significant improvement in yield are achieved.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126603938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
On achieving zero aliasing for modeled faults 对建模故障实现零混叠
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205941
I. Pomeranz, S. Reddy, R. Tangirala
{"title":"On achieving zero aliasing for modeled faults","authors":"I. Pomeranz, S. Reddy, R. Tangirala","doi":"10.1109/EDAC.1992.205941","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205941","url":null,"abstract":"Methods for test-data compression ensuring zero aliasing in logic circuits are described. Aliasing occurs when due to loss of information during compression of the output response, a faulty circuit appears to be fault free. Zero aliasing is guaranteed for a given set of target faults, detected by the test set applied to the circuit. The inability of probabilistic analysis of aliasing to predict coverage of target faults is thus alleviated. Experimental results are presented to support the practicality of the methods proposed in ensuring zero aliasing.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129468743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Test generation for C-testable one-dimensional CMOS ILA's without observable vertical outputs 无可测垂直输出的c -可测一维CMOS ILA的测试生成
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205969
V. Hert, A. van de Goor
{"title":"Test generation for C-testable one-dimensional CMOS ILA's without observable vertical outputs","authors":"V. Hert, A. van de Goor","doi":"10.1109/EDAC.1992.205969","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205969","url":null,"abstract":"Sufficient conditions for C-testability of one-dimensional CMOS iterative logic arrays without vertical outputs are given in the paper. Stuck-open faults in a cell are detected by pairs of input patterns with Hamming distance 1. Procedure that generates pairs or triples of C-test vectors for a CMOS ILA is introduced. The flow table augmentation procedure which requires an addition of at most three columns to an original flow table and enables the design of C-testable CMOS ILA's is given.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127193692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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