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[1992] Proceedings The European Conference on Design Automation最新文献

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Modeling data flow and control flow for high level memory management 为高级内存管理建模数据流和控制流
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205882
M.F.X.B. van Swaaij, F. Franssen, F. Catthoor, H. de Man
{"title":"Modeling data flow and control flow for high level memory management","authors":"M.F.X.B. van Swaaij, F. Franssen, F. Catthoor, H. de Man","doi":"10.1109/EDAC.1992.205882","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205882","url":null,"abstract":"The goal of this paper is to advocate a control flow independent modeling of data flow in applicative algorithm specifications. The model is utilized in the synthesis of ASIC architectures for real-time signal processing applications. It allows for a generalization of control flow transformations which are used to optimize the memory organization at an early stage in the synthesis trajectory. Arguments supporting the inherent amenity of this type of model for use in efficacious memory management optimization schemes will be adduced. A CAD tool is reported which extracts all information related to the model from an applicative algorithm description. Its use is demonstrated on a real-life test vehicle.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126037309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
State assignment for general FSM networks 一般FSM网络的状态分配
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205931
Jia-Jye Shen, Z. Hasan, M. Ciesielski
{"title":"State assignment for general FSM networks","authors":"Jia-Jye Shen, Z. Hasan, M. Ciesielski","doi":"10.1109/EDAC.1992.205931","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205931","url":null,"abstract":"A theoretical formulation of state assignment for general finite state machine (FSM) networks is presented. The goal is to assign binary codes to individual machines so as to satisfy the maximum number of constraints generated from all the machines of the network simultaneously. Using an earlier formulation of a state assignment problem for a single FSM, the state assignment for a general FSM network is formulated as a global input-output encoding problem and solved using the dichotomy covering approach. Given a set of conflict-free input and output constraints for the states/symbolic variables of all submachines, the proposed global dichotomy covering technique produces for each submachine an encoding which maintains the same number of product terms as in the symbolically minimized submachine and satisfies all encoding constraints using a minimum code length.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"192 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114141973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Specification and analysis of timing constraints in signal transition graphs 信号转换图中时序约束的说明与分析
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205943
P. Vanbekbergen, G. Goossens, H. Man
{"title":"Specification and analysis of timing constraints in signal transition graphs","authors":"P. Vanbekbergen, G. Goossens, H. Man","doi":"10.1109/EDAC.1992.205943","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205943","url":null,"abstract":"The introduction of timing constraints in signal transition graphs (STG) is discussed. The possible interpretations of these timing constraints (called the firing semantics) is also discussed. During synthesis it is an important task to calculate the minimum and maximum distance in time between two transitions based on timing information present in the STG. A new recursive algorithm that calculates this time difference is presented. It takes into account some of the firing semantics introduced before. The algorithm finds the correct result for acyclic graphs in a quadratic worst case running time.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130461704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 57
Efficient test set evaluation 高效测试集评估
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205970
H. Wunderlich, M. Warnecke
{"title":"Efficient test set evaluation","authors":"H. Wunderlich, M. Warnecke","doi":"10.1109/EDAC.1992.205970","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205970","url":null,"abstract":"The fault coverage obtained by a set of test patterns is usually determined by expensive fault simulation. Even when using fault dropping techniques, fault simulation provides more information than actually needed. For each fault, the pattern is determined which detects this fault first. This is mainly redundant information if diagnosis is not required. One can dispense with this high resolution and restrict interest to the set of faults which is detected by a set of patterns. It is shown theoretically and practically that this information is obtainable in an highly efficient way.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123820175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Heuristic approach to binate covering problem 二叉覆盖问题的启发式方法
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205906
M. Servít, J. Zamazal
{"title":"Heuristic approach to binate covering problem","authors":"M. Servít, J. Zamazal","doi":"10.1109/EDAC.1992.205906","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205906","url":null,"abstract":"Covering problem is a problem of extraction of a minimum cost subset from a given set that satisfies certain constraints expressed as a Boolean formula in conjunctive normal form. This problem is NP-hard, heuristic methods are thus of interest. The authors present two heuristic methods to finding a nearly minimal solution and compare them to each other. The authors derive the asymptotic complexity of the presented methods and report some computational results obtained for a number of randomly generated covering problems.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114557890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Flow-a concurrent methodology manager flow—并发方法管理器
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205885
Y. Kashai
{"title":"Flow-a concurrent methodology manager","authors":"Y. Kashai","doi":"10.1109/EDAC.1992.205885","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205885","url":null,"abstract":"The Flow system is used to define methodology for ULSI design tasks in a formal way. It provides a concurrent environment in which such tasks are carried out automatically. The automatic execution of tasks in the Flow system utilize a set of workstations as computing resources. This paper describes the motivation for the development of Flow, the semantics used for methodology definition and the Flow system that carries out the defined tasks. Results demonstrating the systems robustness and superior load balancing technique are presented.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121292641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Concatenable cellular automata register design for built-in self-test 可连接的细胞自动机寄存器设计，用于内置自检
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205915
A. Hlawiczka, M. Kopec
{"title":"Concatenable cellular automata register design for built-in self-test","authors":"A. Hlawiczka, M. Kopec","doi":"10.1109/EDAC.1992.205915","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205915","url":null,"abstract":"The paper describes the principles of concatenations of cellular automata based LFSRs (MISR). It proves some theorems and lemmas which show if a certain cellular automata based register has a reducible polynomial of the form xg(x) or (x+l)h(x). Further it answers the question how to find a minimal set of standard CAD system cells to permit the construction of various length and various primitive characteristic polynomial cellular automata based LFSRs (MISRs). The paper also lists many examples of d-bit sliced cellular automata register families which allow for the building of concatenations having primitive polynomials.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122615710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An automatic layout generator for analog circuits 模拟电路的自动布局生成器
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205989
J. Conway, G. G. Schrooten
{"title":"An automatic layout generator for analog circuits","authors":"J. Conway, G. G. Schrooten","doi":"10.1109/EDAC.1992.205989","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205989","url":null,"abstract":"A 'design by example' approach to automatic layout generation for analog circuits is presented. This approach uses a sample layout, the template, to graphically capture an expert's knowledge of analog device placement and routing for a given module type. To generate a module, one supplies the required electrical parameters for each device and a geometrical constraint on the module's shape e.g. a desired aspect ratio. Using exhaustive floorplan area optimisation techniques, the tool then determines the optimum shape of each device so as to satisfy the user's geometrical constraint. Subsequently, layout is generated by transforming (via compaction) the template into a module, substituting the devices in the template by newly generated devices with the user-supplied electrical parameters and the determined geometrical shapes. This technique produces good quality layout in reasonable amount of time, by availing of the expert designer knowledge embedded in the template and by taking analog specific features like device matching and merging into account during the layout transformation phase. This approach is illustrated using an n-type super MOS transistor circuit generator.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116393115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Derivation of high quality tests for large heterogeneous circuits: floating-point operations 大型异构电路的高质量测试的推导:浮点运算
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205954
U. Sparmann
{"title":"Derivation of high quality tests for large heterogeneous circuits: floating-point operations","authors":"U. Sparmann","doi":"10.1109/EDAC.1992.205954","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205954","url":null,"abstract":"The problem of deriving high quality tests for fast combinational floating-point realizations is investigated. Floating-point circuits are heterogeneous, consisting of a large number of regular and irregular modules. Thus, the test strategy applied combines specialized structure based methods and universal test generation. In order to guarantee sufficient controllability and observability of embedded modules, small hardware modifications are proposed. As a result, the authors obtain optimal-time floating-point circuits for arbitrary operand lengths which can be tested completely with respect to a strong fault model by a minimal number of test patterns.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132366836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Rule-based analog circuit design 基于规则的模拟电路设计
[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI: 10.1109/EDAC.1992.205981
R. Klinke, H.-L. Fiedler, B. Hosticka, R. Kokozinski, I. Munster
{"title":"Rule-based analog circuit design","authors":"R. Klinke, H.-L. Fiedler, B. Hosticka, R. Kokozinski, I. Munster","doi":"10.1109/EDAC.1992.205981","DOIUrl":"https://doi.org/10.1109/EDAC.1992.205981","url":null,"abstract":"A prototype of a rule-based environment for analog integrated circuit design is presented. It features a hierarchical design style, multifunctionality and adaption capability for its knowledge bases. The prototype called AC/DC has been realized as a set of cooperating tools for design and verification. The overall system can act like an automatic tool as well as a design assistant. In its current version it can design CMOS operational amplifiers and switched-capacitor (SC)-filters.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127456742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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