Modeling data flow and control flow for high level memory management

The goal of this paper is to advocate a control flow independent modeling of data flow in applicative algorithm specifications. The model is utilized in the synthesis of ASIC architectures for real-time signal processing applications. It allows for a generalization of control flow transformations which are used to optimize the memory organization at an early stage in the synthesis trajectory. Arguments supporting the inherent amenity of this type of model for use in efficacious memory management optimization schemes will be adduced. A CAD tool is reported which extracts all information related to the model from an applicative algorithm description. Its use is demonstrated on a real-life test vehicle.<>