{"title":"An automatic layout generator for analog circuits","authors":"J. Conway, G. G. Schrooten","doi":"10.1109/EDAC.1992.205989","DOIUrl":null,"url":null,"abstract":"A 'design by example' approach to automatic layout generation for analog circuits is presented. This approach uses a sample layout, the template, to graphically capture an expert's knowledge of analog device placement and routing for a given module type. To generate a module, one supplies the required electrical parameters for each device and a geometrical constraint on the module's shape e.g. a desired aspect ratio. Using exhaustive floorplan area optimisation techniques, the tool then determines the optimum shape of each device so as to satisfy the user's geometrical constraint. Subsequently, layout is generated by transforming (via compaction) the template into a module, substituting the devices in the template by newly generated devices with the user-supplied electrical parameters and the determined geometrical shapes. This technique produces good quality layout in reasonable amount of time, by availing of the expert designer knowledge embedded in the template and by taking analog specific features like device matching and merging into account during the layout transformation phase. This approach is illustrated using an n-type super MOS transistor circuit generator.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"144 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1992] Proceedings The European Conference on Design Automation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAC.1992.205989","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 34
Abstract
A 'design by example' approach to automatic layout generation for analog circuits is presented. This approach uses a sample layout, the template, to graphically capture an expert's knowledge of analog device placement and routing for a given module type. To generate a module, one supplies the required electrical parameters for each device and a geometrical constraint on the module's shape e.g. a desired aspect ratio. Using exhaustive floorplan area optimisation techniques, the tool then determines the optimum shape of each device so as to satisfy the user's geometrical constraint. Subsequently, layout is generated by transforming (via compaction) the template into a module, substituting the devices in the template by newly generated devices with the user-supplied electrical parameters and the determined geometrical shapes. This technique produces good quality layout in reasonable amount of time, by availing of the expert designer knowledge embedded in the template and by taking analog specific features like device matching and merging into account during the layout transformation phase. This approach is illustrated using an n-type super MOS transistor circuit generator.<>