Test generation for C-testable one-dimensional CMOS ILA's without observable vertical outputs

Abstract

Sufficient conditions for C-testability of one-dimensional CMOS iterative logic arrays without vertical outputs are given in the paper. Stuck-open faults in a cell are detected by pairs of input patterns with Hamming distance 1. Procedure that generates pairs or triples of C-test vectors for a CMOS ILA is introduced. The flow table augmentation procedure which requires an addition of at most three columns to an original flow table and enables the design of C-testable CMOS ILA's is given.<>