{"title":"对建模故障实现零混叠","authors":"I. Pomeranz, S. Reddy, R. Tangirala","doi":"10.1109/EDAC.1992.205941","DOIUrl":null,"url":null,"abstract":"Methods for test-data compression ensuring zero aliasing in logic circuits are described. Aliasing occurs when due to loss of information during compression of the output response, a faulty circuit appears to be fault free. Zero aliasing is guaranteed for a given set of target faults, detected by the test set applied to the circuit. The inability of probabilistic analysis of aliasing to predict coverage of target faults is thus alleviated. Experimental results are presented to support the practicality of the methods proposed in ensuring zero aliasing.<<ETX>>","PeriodicalId":285019,"journal":{"name":"[1992] Proceedings The European Conference on Design Automation","volume":"85 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"On achieving zero aliasing for modeled faults\",\"authors\":\"I. Pomeranz, S. Reddy, R. Tangirala\",\"doi\":\"10.1109/EDAC.1992.205941\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Methods for test-data compression ensuring zero aliasing in logic circuits are described. Aliasing occurs when due to loss of information during compression of the output response, a faulty circuit appears to be fault free. Zero aliasing is guaranteed for a given set of target faults, detected by the test set applied to the circuit. The inability of probabilistic analysis of aliasing to predict coverage of target faults is thus alleviated. Experimental results are presented to support the practicality of the methods proposed in ensuring zero aliasing.<<ETX>>\",\"PeriodicalId\":285019,\"journal\":{\"name\":\"[1992] Proceedings The European Conference on Design Automation\",\"volume\":\"85 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-03-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1992] Proceedings The European Conference on Design Automation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAC.1992.205941\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1992] Proceedings The European Conference on Design Automation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAC.1992.205941","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Methods for test-data compression ensuring zero aliasing in logic circuits are described. Aliasing occurs when due to loss of information during compression of the output response, a faulty circuit appears to be fault free. Zero aliasing is guaranteed for a given set of target faults, detected by the test set applied to the circuit. The inability of probabilistic analysis of aliasing to predict coverage of target faults is thus alleviated. Experimental results are presented to support the practicality of the methods proposed in ensuring zero aliasing.<>
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