A parallel switch-level simulator for mixed analog-digital circuit simulation

Abstract

Presents a parallel event-driven switch-level simulator intended for medium-grain multicomputers. The chosen parallel algorithm ensures that node voltages are always defined. This avoids problems with undefined node states and makes the simulator suitable for mixed analog-digital simulation. The active devices are modeled as piecewise-constant current sources, which gives high timing accuracy and enables simulation of other circuit technologies than MOS logic. Experimental results from simulation of a CMOS synchronous counter run on parallel workstations are presented.<>