Logic synthesis for arithmetic circuits using the Reed-Muller representation

A procedure for multi-level Reed-Muller minimization has been developed which introduces a Reed-Muller factored form, and uses algebraic algorithms for factorization, decomposition, resubstitution, collapsing, and extraction of common cubes and subexpressions. The procedure has been used to design some arithmetic circuits using a gate library containing a wide range of gates, and the resulting circuits were compared with some designed using MisII. The circuits designed using the Reed-Muller system were over 20 percent smaller and between 25 and 50 percent faster.<>