测试嵌入式单和多端口ram使用BIST和边界扫描

[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI:10.1109/EDAC.1992.205914

V. Castro Alves, M. Lubaszewski, M. Nicolaidis, B. Courtois

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引用次数: 1

摘要

本文提出了一种通用的BIST方案，用于测试嵌入在非常复杂的asic中的ram(单端口和多端口)。一个由IEEE边界扫描(BS)标准驱动的简单的BIST电路被同时测试的所有存储器共享。测试开发时间的减少和与BS.>的连接极大地补偿了面积开销

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Testing embedded single and multi-port RAMs using BIST and boundary scan

The paper presents a general BIST scheme for the test of RAMs (single and multi-port) embedded in very complex ASICs. A simple BIST circuit driven by the IEEE standard for the boundary scan (BS) is shared by all the memories that are tested simultaneously. The area overhead is greatly compensated by the test development time reduction and the link with BS.<>

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[1992] Proceedings The European Conference on Design Automation

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