并行仿真的VHDL并行提取与程序重构

[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI:10.1109/EDAC.1992.205899

B. Vellandi, M. Lightner

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引用次数: 7

摘要

作者通过将仿真模型分解为更小的并行执行的计算单元，并通过并行化仿真支持函数，在VHDL仿真期间获得了并行性的总体增加。作者实现了有针对性的大规模并行架构。在SIMD连接机上进行了仿真实验和仪器测试。

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Parallelism extraction and programme restructuring of VHDL for parallel simulation

The authors obtained an overall increase in parallelism during VHDL simulation by decomposing simulation models into smaller computational units to be executed in parallel and by parallelizing the simulation support functions. The authors implementation targeted massively parallel architectures. Simulation experimentation and instrumentation was done on the SIMD Connection Machine.<>

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来源期刊

[1992] Proceedings The European Conference on Design Automation

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