An alternative to fault simulation for delay-fault diagnosis

Abstract

Delay testing is a test procedure to verify the timing performance of manufactured digital circuits. A diagnosis process is often implemented after the detection of a fault in a circuit. Unfortunately, existing methodologies for locating delay defects on digital circuits have shown certain deficiencies. A new method for delay fault diagnosis, based on critical path tracing from a symbolic simulation, is presented. This method needs to consider only the fault-free circuit and provides perfectly reliable results. It does not require timing evaluations and can be very accurate.<>