Energy minimization based delay testing

Abstract

The authors present a novel method for generating robust and non-robust tests for path or gate delay faults in scan and hold type of sequential circuits. The relationship between input and output signal states of a logic gate for an arbitrary pair of input vectors is expressed through an energy function such that minimum-energy states correspond to signal values that are consistent with the gate logic function for both input vectors. The energy function for the circuit is the summation of individual gate energy functions. It implicitly contains information about hazards. For a given delay fault, the energy function is suitably modified so that minimum-energy states are guaranteed to be hazard-free or robust delay tests. Results on sequential benchmark circuit are given.<>