多种充放电路径对BiCMOS逻辑电路测试的影响

[1992] Proceedings The European Conference on Design Automation Pub Date : 1992-03-16 DOI:10.1109/EDAC.1992.205996

K. Roy, M. Levitt, J. Abraham

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引用次数: 3

摘要

由于在BiCMOS逻辑门的输出节点上存在多条充电或放电路径，许多实际的开路和短路故障表现为上升或下降时间延迟故障，而不改变电路的功能。基于电路级故障，已经观察到，对于BiCMOS逆变器的相同故障集，延迟故障测试可以产生高达92%的故障覆盖率，而卡滞测试产生的故障覆盖率为29%。讨论了这种主要失效模式的含义，并提出了一种门级可测试性设计(DFT)方案。

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The effect of multiple charge-discharge paths on testing of BiCMOS logic circuits

Due to the presence of multiple paths to charge or discharge the output node of a BiCMOS logic gate, many of the realistic open and short faults appear as rise or fall time delay faults without changing the functionality of the circuit. Based on circuit level faults, it has been observed that delay fault tests can produce a fault coverage as high as 92% compared to 29% produced by stuck-at tests, for the same set of faults for a BiCMOS inverter. The implications of this dominant failure mode are discussed and a gate level design-for-testability (DFT) scheme is presented.<>

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[1992] Proceedings The European Conference on Design Automation

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