2010 IEEE International Test Conference最新文献_第3页

Low cost at-speed testing using On-Product Clock Generation compatible with test compression 使用与测试压缩兼容的产品时钟生成进行低成本的高速测试

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699276

B. Keller, K. Chakravadhanula, Brian Foutz, V. Chickermane, R. Malneedi, T. Snethen, V. Iyengar, D. Lackey, Gary Grise

引用次数: 7

Optimization of burn-in test for many-core processors through adaptive spatiotemporal power migration 基于自适应时空功率迁移的多核处理器老化测试优化

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699205

M. Cho, N. Sathe, A. Raychowdhury, S. Mukhopadhyay

引用次数: 11

Package test interface fixture considering low cost solution, high electrical performance, and compatibility with fine pitch packages 封装测试接口夹具考虑低成本解决方案，高电气性能，并与小间距封装兼容

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699264

Ki-Jae Song, Hunkyo Seo, Sang-hyun Ko

引用次数: 1

Using context based methods for test data compression 使用基于上下文的方法进行测试数据压缩

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699301

Sara Karamati, Z. Navabi

引用次数: 0

STIL P1450.4: A standard for test flow specification astm P1450.4:测试流程规范的标准

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699254

Jim O'Reilly, A. Khoche, E. Wahl, B. Parnas

引用次数: 1

A low-cost ATE phase signal generation technique for test applications 用于测试应用的低成本ATE相位信号生成技术

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699202

S. Aouini, Kun Chuai, G. Roberts

{"title":"A low-cost ATE phase signal generation technique for test applications","authors":"S. Aouini, Kun Chuai, G. Roberts","doi":"10.1109/TEST.2010.5699202","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699202","url":null,"abstract":"In this article, an accurate and low-cost clock delay generation system integrated in an automated test equipment (ATE) environment is presented. The input to this system is entirely digital and is driven by a single clock, which can be programmed from the ATE High Speed Digital (HSD) unit. Moreover, the digital input patterns can easily be generated in software off-line; hence, making this system ideal for automated test routines. The system is first discussed and characterized in Matlab under static and dynamic operating conditions. For the static behavior, the impact of the various design tradeoffs on the time resolution is investigated. With regards to the dynamic behavior, the linearity is assessed spectrally with a sinusoidal input and statistically using a Gaussian noise signal. A discrete prototype board is built to validate the correct operation of the system mounted on an ATE to function as a whole. With proper compensation and calibration, a delay resolution of 15 ps was achieved over an 8.4 ns range using a low-speed reference clock running at 16.67 MHz. It is shown through clock scaling that this resolution can improve in direct proportion to increases in the clock frequency.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122900546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Path coverage based functional test generation for processor marginality validation 基于路径覆盖的处理器边缘性验证功能测试生成

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699257

S. Natarajan, A. Krishnamachary, E. Chiprout, R. Galivanche

引用次数: 9

Testing of latch based embedded arrays using scan tests 使用扫描测试测试基于锁存器的嵌入式阵列

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699210

Fan Yang, S. Chakravarty

引用次数: 5

Post-manufacturing ECC customization based on Orthogonal Latin Square codes and its application to ultra-low power caches 基于正交拉丁方码的制造后ECC定制及其在超低功耗缓存中的应用

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699221

Rudrajit Datta, N. Touba

{"title":"Post-manufacturing ECC customization based on Orthogonal Latin Square codes and its application to ultra-low power caches","authors":"Rudrajit Datta, N. Touba","doi":"10.1109/TEST.2010.5699221","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699221","url":null,"abstract":"The paper proposes the idea of implementing a general multi-bit error correcting code (ECC) based on Orthogonal Latin Square (OLS) Codes in on-chip hardware, but then selectively, on a chip-by-chip basis, using only a subset of the code's check bits (subset of the rows in its H-matrix) depending on the defect map for a particular chip. The defect map is obtained from a memory characterization test which identifies which cells are defective or marginal. The idea proposed here is that if a general t-bit error correcting code is implemented in hardware and requires cfull=n−k check bits for k information bits, then once the defect map is known, the defective cells become erasures w.r.t. the ECC. This fact can be used to select only a subset of the n−k rows in the H-matrix which are sufficient to provide the desired error detection/correction capability in the presences of the known erasures. By selectively reducing the number of rows in the H-matrix, the number of check bits that are actually stored and used, cused, can be restricted and the corresponding unused ECC hardware disabled. This reduces the check bit storage requirements and hence frees up more of the cache for storing data and improving performance. This strategy is applied to the problem of providing reliable cache operation in ultra-low voltage modes, and results indicate that with the proposed post-manufacturing ECC customization, a fraction of the number of check bits are required compared to using a full OLS code for handling a particular defect rate.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124083785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Adaptive test flow for mixed-signal/RF circuits using learned information from device under test 混合信号/射频电路的自适应测试流程，使用从被测设备学习到的信息

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699271

E. Yilmaz, S. Ozev, K. Butler

{"title":"Adaptive test flow for mixed-signal/RF circuits using learned information from device under test","authors":"E. Yilmaz, S. Ozev, K. Butler","doi":"10.1109/TEST.2010.5699271","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699271","url":null,"abstract":"Despite their small size, analog/mixed-signal circuits start with an extensive set of parameters to test for. During production ramp up, most of these tests are dropped using statistical analysis techniques based on the dropout patterns. While effective in reducing the number of tests, this approach treats each device in an identical manner. As the statistical diversity of the devices increases due to increasing process variations, such homogeneous testing approaches may prove to be inefficient. After a number of initial measurements, device-specific information is available, which can provide clues as to where in the process space that device falls. Using this information, the test set for each device can be tailored with respect to its own statistical information. In this paper, we present an adaptive test flow for mixed-signal circuits that aims at optimizing the test set per-device basis so that more test resources can be devoted to marginal devices whereas devices that fall in the middle of the process space are passed with less testing. We also include provisions to identify potentially defective devices and test them more extensively since these devices do not conform to learned collective information. We conduct experiments on an LNA circuit in simulations and apply our techniques to production data of two distinct industrial circuits. Both the simulation results and the results on large-scale production data show that adaptive test provides the best trade-off between test time and test quality as measured in terms of defective parts per million.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127828469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30