2010 IEEE International Test Conference最新文献_第10页

Design and test of latch-based circuits to maximize performance, yield, and delay test quality 设计和测试基于锁存器的电路，以最大限度地提高性能，良率和延迟测试质量

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699209

K. Chung, S. Gupta

{"title":"Design and test of latch-based circuits to maximize performance, yield, and delay test quality","authors":"K. Chung, S. Gupta","doi":"10.1109/TEST.2010.5699209","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699209","url":null,"abstract":"The performance benefits of latch-based circuits have been known for some time. These benefits are due to the timing flexibility and skew-tolerance enabled by the ability of combinational logic blocks to borrow time from each other across the intervening level-sensitive latches. It has also been known that, by accommodating higher levels of process variations and small delay-defects, time borrowing can enhance yield at high clock frequencies. The main roadblock was that conventional scan-based delay testing approaches cannot be adapted from flip-flop-based (FF-based) circuits to latch-based circuits in a manner that can harvest above benefits. Recently, a scan-based delay testing approach has been proposed for latch-based circuits which holds the promise of harvesting the abovementioned performance and yield benefits. In this paper, we investigate two main questions. First, can this new scan-based delay testing approach provide high coverage of delay faults for all latch-based circuits- independent of the pervasiveness of time borrowing? Second, how do we design the circuit and develop tests so as to harvest maximal performance and yield benefits? We prove that the above delay testing approach for latch-based circuits obtains the maximum path delay fault coverage possible for any scan-based test methodology and this test quality is always greater than (or equal to) that obtainable for the corresponding FF-based circuit. We derive the conditions to satisfy during design and test development to guarantee maximal performance and yield benefits of latch-based designs vs. their FF-based counterparts. Hence, we show for the first time that it is possible for latch-based circuits to provide higher performance and yield and also to certify the higher performance via high delay test quality.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130362682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains 时钟控制架构和ATPG，用于减少具有多个时钟域的SoC设计中的模式计数

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699211

T. Waayers, R. Morren, X. Lin, M. Kassab

引用次数: 6

Experiences with parametric BIST for production testing PLLs with picosecond precision 具有皮秒级生产测试锁相环的参数化测试经验

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699243

Rakesh Kinger, Swetha Narasimhawsamy, S. Sunter

引用次数: 16

A high linearity compact timing vernier for CMOS timing generator 一种用于CMOS定时发生器的高线性紧凑定时游标

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699174

Jun Kohno, Tatsuro Akiyama, D. Kato, M. Imamura

引用次数: 6

Evaluation techniques of frequency-dependent I/Q imbalances in wideband quadrature mixers 宽带正交混频器中频率相关I/Q不平衡的评估技术

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699223

Koji Asami, Toshiaki Kurihara, Yushi Inada

引用次数: 4

Highly efficient parallel ATPG based on shared memory 基于共享内存的高效并行ATPG

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699236

X. Cai, P. Wohl, J. Waicukauski, Pramod Notiyath

引用次数: 24

Fault models and test methods for subthreshold SRAMs 亚阈值sram的故障模型和测试方法

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699245

Chen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, M. Chao, Rei-Fu Huang

引用次数: 8

Complete testing of receiver jitter tolerance 完成接收机抖动公差测试

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699175

T. Lyons

引用次数: 5

Hard to find, easy to find systematics; just find them 难找的，容易找的;找到他们

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699240

R. Desineni, L. Pastel, M. Kassab, Robert Redburn

引用次数: 7

Detecting and diagnosing open defects 检测和诊断开放缺陷

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699303

Dat Tran, L. Winemberg, D. Carder, X. Lin, Joe LeBritton, B. Swanson

引用次数: 0