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2010 IEEE International Test Conference最新文献

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Commanded Test Access Port operations 命令测试访问端口操作
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699261
Lee Whetse
{"title":"Commanded Test Access Port operations","authors":"Lee Whetse","doi":"10.1109/TEST.2010.5699261","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699261","url":null,"abstract":"This paper describes a method of enabling IEEE 1149.1 Test Access Ports to perform at-speed “Update & Capture” and “Shift & Capture” operations in response to command inputs.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125399011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling TSV open defects in 3D-stacked DRAM 3d堆叠DRAM中TSV开放缺陷的建模
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699217
Li Jiang, Yuxi Liu, L. Duan, Yuan Xie, Q. Xu
{"title":"Modeling TSV open defects in 3D-stacked DRAM","authors":"Li Jiang, Yuxi Liu, L. Duan, Yuan Xie, Q. Xu","doi":"10.1109/TEST.2010.5699217","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699217","url":null,"abstract":"Three-dimensional (3D) stacking using through silicon vias (TSVs) is a promising solution to provide low-latency and high-bandwidth DRAM access from microprocessors. The large number of TSVs implemented in 3D DRAM circuits, however, are prone to open defects and coupling noises, leading to new test challenges. Through extensive simulation studies, this paper models the faulty behavior of TSV open defects occurred on the wordlines and the bitlines of 3D DRAM circuits, which serves as the first step for efficient and effective test and diagnosis solutions for such defects.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121641074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Estimating defect-type distributions through volume diagnosis and defect behavior attribution 通过体积诊断和缺陷行为归因估计缺陷类型分布
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699270
Xiaochun Yu, R. D. Blanton
{"title":"Estimating defect-type distributions through volume diagnosis and defect behavior attribution","authors":"Xiaochun Yu, R. D. Blanton","doi":"10.1109/TEST.2010.5699270","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699270","url":null,"abstract":"We propose a methodology that effectively estimates the defect-type distribution that affects a design fabricated in a given manufacturing process. Understanding the distribution can improve design quality, test quality, and the manufacturing process itself. The methodology is composed of i) an improved approach for identifying the signal lines relevant to defect activation at each site reported by diagnosis, ii) a new behavior attribution method, and iii) a novel approach to estimate the defect-type distribution. The efficacy of this methodology is validated using circuit-level simulation experiments. The results show that the method achieves an average accuracy of 94% in identifying signal lines that are relevant to the activation of a defect. When estimating defect-type distribution for a population affected by a variety of defects, the average estimation accuracy is 92% with ideal diagnosis. With a realistic diagnosis (i.e., the inherent ambiguity of diagnosis is accounted for), the estimated defect-type distribution is 85% accurate, on average.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131981613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
DFM aware bridge pair extraction for manufacturing test development 面向制造测试开发的DFM感知桥对提取
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699304
Sarveswara Tammali, V. Khatri, G. Shanmugam, M. Terry
{"title":"DFM aware bridge pair extraction for manufacturing test development","authors":"Sarveswara Tammali, V. Khatri, G. Shanmugam, M. Terry","doi":"10.1109/TEST.2010.5699304","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699304","url":null,"abstract":"We propose a novel method to extract bridge pairs for manufacturing test development based on litho hotspots obtained from DFM (Design-For-Manufacturability) litho models. Litho hotspots are locations in a physical layout in which the lithography process margin is relatively small. We use a DFM lithography simulator to identify litho hotspots and map them onto the design database to identify the associated nets. These nets are then used to select prioritized bridging pairs from extracted capacitive coupling based bridge pairs.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131407091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Concurrent test planning 并行测试计划
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699255
Bethany Van Wagenen, E. Seng
{"title":"Concurrent test planning","authors":"Bethany Van Wagenen, E. Seng","doi":"10.1109/TEST.2010.5699255","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699255","url":null,"abstract":"Testing multiple device functions in parallel can yield significant test time and cost of test reductions. This paper discusses the planning process and algorithms required to realize an efficient and achievable concurrent test plan.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116473534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Constrained ATPG for functional RTL circuits using F-Scan 使用f -扫描的功能RTL电路的约束ATPG
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699265
M. Obien, S. Ohtake, H. Fujiwara
{"title":"Constrained ATPG for functional RTL circuits using F-Scan","authors":"M. Obien, S. Ohtake, H. Fujiwara","doi":"10.1109/TEST.2010.5699265","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699265","url":null,"abstract":"In this paper, we present an approach to constrained automatic test pattern generation (ATPG) for functional circuits at register-transfer level (RTL) with the help of a design-for-testability (DFT) technique called F-scan. The DFT method optimally utilizes existing functional elements and paths for test, thus it effectively reduces the hardware overhead due to test. This is done by arranging all registers in the circuit into F-scan-paths and augmenting necessary circuitry at RTL. After DFT, we create the constraint test generation model of the circuit based on the test environment obtained from the information of F-scan-paths. With this approach, only the applicable test vectors to the F-scan-paths can be generated and test application time is kept at the minimum. The comparison of F-scan with the performance of gate-level full scan design is shown through the experimental results.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121124272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Solutions for undetected shorts on IEEE 1149.1 self-monitoring pins IEEE 1149.1自监控引脚上未检测到短路的解决方案
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699259
C. Clark, David Dubberke, K. Parker, Bill Tuthill
{"title":"Solutions for undetected shorts on IEEE 1149.1 self-monitoring pins","authors":"C. Clark, David Dubberke, K. Parker, Bill Tuthill","doi":"10.1109/TEST.2010.5699259","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699259","url":null,"abstract":"This paper presents the problem of undetected shorts on IEEE 1149.1 compliant self-monitoring pins. Unidirectional and bidirectional self-monitoring pins may contain sufficient series termination resistance and low enough voltage swings such that shorts between two pins become resistively isolated from the receivers and therefore are undetected during wiring interconnect tests. Potential solutions to mitigate the problem are offered.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120988920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ADC linearity testing method with single analog monitoring port ADC线性度测试方法，单模拟监测端口
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699244
T. Kawachi, K. Irie
{"title":"ADC linearity testing method with single analog monitoring port","authors":"T. Kawachi, K. Irie","doi":"10.1109/TEST.2010.5699244","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699244","url":null,"abstract":"We propose an ADC linearity testing method with a single analog monitoring port. This method enables direct measurement of code transitions without clocking and digital signal processing. We analyzed code transition measurement errors caused by additional monitoring circuits, and verified that the errors are less than 0.1LSB with simulations. We applied the proposed testing method to laser wafer trimming (LWT) for ADC linearity improvement, and achieved integral non-linearity (INL) 0.26LSB and differential non-linearity (DNL) 0.30LSB respectively.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126015472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A practical scan re-use scheme for system test 一个实用的系统测试扫描重用方案
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699306
Kelly Lee
{"title":"A practical scan re-use scheme for system test","authors":"Kelly Lee","doi":"10.1109/TEST.2010.5699306","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699306","url":null,"abstract":"This paper presents the work at Texas Instruments for achieving an efficient scan test and IC failure analysis at system level with the advanced scan compression technology. Unlike other approaches that are associated with longer test time, difficult implementation or limited failure analysis capability, the proposed system scan scheme is simply an add-on with ad-hoc scan technologies. The result shows that an ATE-like scan test coverage, including both StuckAt and TFT, was delivered, a more accurate failure diagnostics was achieved.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127657770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
AXIe®: Open architecture test system standard AXIe®:开放式架构测试系统标准
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699293
A. Czamara
{"title":"AXIe®: Open architecture test system standard","authors":"A. Czamara","doi":"10.1109/TEST.2010.5699293","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699293","url":null,"abstract":"A new open architecture test system standard, AXIe<sup>®</sup> is introduced. A summary of the two initial standards is presented with a focus on explaining why a standard is needed, and detailing success metrics applicable to ATE testing, including the impact of AXIe<sup>®</sup> on cost of test.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130347961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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